Abstract: Routing between multiple hosts and adapters in a PCI environment is provided by a method and system. A Destination Identification (DID) field is inserted in a field of the PCI bus address (PBA) of transaction packets dispatched through PCI switches. A particular DID is associated with a particular host or system image, and thus identifies the physical or virtual end point of the packets. The method and system may track connections such that when particular host of a root node becomes connected to a specified switch, a PCI Configuration Master (PCM), residing in one of the root nodes, is operated to enter a destination identifier or DID into a table. The DID is then inserted in the PBA of packets directed through the specified switch from the particular host to one of the adapters.

Abstract: Registering memory space for an application is performed. One or more open calls are received from an application to access one or more input/output (I/O) devices. Responsive to receiving the one or more open calls, one or more I/O map and pin calls are sent in order to register memory space for the one or more I/O devices within at least one storage area that will be accessed by the application. A verification is made as to whether the memory space to be registered is associated with the application. Responsive to the memory space being associated with the application, at least one virtual I/O bus address is received for each registered memory space of the one or more I/O devices. At least one I/O command is executed using the at least one virtual I/O bus address without intervention by an operating system or operating system image.

Abstract: A method and apparatus is provided for routing error messages in a distributed computer system comprising multiple root nodes, and further comprising one or more PCI switches and one or more I/O adapters, wherein each root node includes one or more system images. In one useful embodiment, a method is provided for routing I/O error messages to root nodes respectively associated with the errors contained in the messages. The method includes detecting occurrence of an error at a specified one of the adapters, wherein the error affects one of the system images, and generating an error message at the specified adapter. The method further comprises routing the error message from the specified adapter to the particular root node that includes the affected system image. The error message is then selectively processed at the particular root node, in order to identify the affected system image.

Abstract: A method mechanism is provided for communication between host systems using a transaction protocol and shared memories. Shared memories are initialized based on a discovery process in a communication fabric such that at least one endpoint has address ranges in shared memories of at least two host systems. A transaction oriented protocol may be established for using the shared memories of the host systems to communicate between root complexes and endpoints of the same or different host systems. The transaction oriented protocol specifies a series of transactions to be performed by the various elements, e.g., root complex or endpoint, to push or pull data. Various combinations of push and pull transactions may be utilized.

Abstract: A mechanism is provided for communication between host systems using a queuing system and shared memories. Memory address spaces of the host systems are initialized such that endpoints may be accessible by root complexes across host systems. These memory address spaces may then be used to allow system images, and their corresponding applications, associated with these root complexes to communicate with the endpoints using a queuing system. Such a queuing system may comprise queue structures having doorbell structures for providing information about the queue entries in the queue structures. Queue elements may be generated and added to the queue structures, and the doorbell structure may be written to, in order to thereby inform an endpoint or root complex that queue elements are available for processing. DMA operations may be performed to retrieve the queue elements and the data corresponding to the queue elements.

Abstract: Mechanisms for hot-plug/remove of a new component in a running communication fabric, such as a PCIe fabric, are provided. With these mechanisms, the addition of a new component in the fabric is detected and an event is sent to a multiple root fabric configuration manager. The multiple root fabric configuration manager gathers information about the new component and updates its I/O component tree structure in its configuration data structure to include the new component. The new component may then be utilized via the updated configuration data structure. When a component is to be removed, the multiple root fabric configuration manager receives an event indicating the component to be removed, determines which branches of the tree structure are affected by the removal, and updates its configuration data structure accordingly to remove the component and its associated components from the virtual plane of the removed component.

Abstract: A computer-implemented method, apparatus, and computer program product are disclosed in a data processing environment that includes host computer systems that are coupled to adapters utilizing a switched fabric for routing packets between the host computer systems and the adapters. A unique destination identifier is assigned to one of the host computer systems. A portion of a standard format packet destination address is selected. Within a particular packet, the portion is set equal to the unique identifier that is assigned to the host computer system. The particular packet is then routed through the fabric to the host computer system using the unique destination identifier.

Abstract: Mechanisms for migration of a virtual endpoint from one virtual plane to another are provided. With these mechanisms, when a management application requests migration of a virtual endpoint (VE) from one virtual plane (VP) to another, a fabric manager provides an input/output virtualization intermediary (IOVI) with an interrupt to perform a stateless migration. The IOVI quiesces outstanding requests to the virtual functions (VFs) of the VE, causes a function level reset of the VFs, deconfigures addresses in intermediary switches corresponding to the VP, and informs the fabric manager that a destination migration is requested. The fabric manager sends an interrupt to the destination IOVI which performs a function level reset of the destination VFs and reprograms the intermediary switches with the addresses of the destination VP. The destination VFs may then be placed in an active state.

Abstract: Mechanisms for differentiating traffic types per host system blade in a multi-root PCI Express environment are provided. The mechanisms generate a first mapping data structure that, for each single-root virtual hierarchy in the multi-root data processing system, associates a plurality of traffic classes with a plurality of priority groups and maps each traffic class in the plurality of traffic classes to a corresponding virtual channel in a plurality of virtual channels. Moreover, a second mapping data structure is generated that maps each virtual channel in the plurality of virtual channels to corresponding per host system blade virtual links in a plurality of virtual links of the multi-root data processing system. Traffic of a particular priority group is routed from a single-root virtual hierarchy to a particular virtual link in the plurality of the virtual links based on the first mapping data structure and second mapping data structure.

Abstract: A hypervisor, during device discovery, has code which can examine the south-side management data structure in an adapter's configuration space and determine the type of device which is being configured. The hypervisor may copy the south-side management data structure to a hardware management console (HMC) and the HMC can populate the data structure with south-side data and then pass the structure to the hypervisor to replace the data structure on the adapter. In another embodiment the hypervisor may copy the data structure to the HMC and the HMC can instruct the hypervisor to fill-in the data structure, a virtual function at a time, with south-side management data associations. The administrator can assign south-side data, such as a MAC address for a virtual instance of an Ethernet device, to LPARs sharing the adapter. Thus, a standard way to manage the south-side data of virtual functions is provided.

Abstract: In one embodiment, a computer-implemented method for creating redundant system configurations is presented. The computer-implemented method creates a set of virtual function path authorization tables, and receives a request from a requester to provide requested data from a virtual function wherein the virtual function is performed by a single root or a multi-root peripheral component interconnect device. Further a receive buffer is created in a selected address range in a set of addresses ranges as well as a virtual function work queue entry for the virtual function containing an address of the receive buffer in the selected address range. Responsive to a determination that the virtual function is authorized, writing the requested data into the receive buffer of the selected address range in the one or more systems, and responsive to writing the requested data, issuing a notice of completion to the requester.

Abstract: Mechanisms for differentiating traffic types in a multi-root PCI Express environment are provided. The mechanisms generate a first mapping data structure that, for each single-root virtual hierarchy in the multi-root data processing system, associates a plurality of traffic classes with a plurality of priority groups and maps each traffic class in the plurality of traffic classes to a corresponding virtual channel in a plurality of virtual channels. Moreover, a second mapping data structure is generated that maps each virtual channel in the plurality of virtual channels to corresponding virtual link in a plurality of virtual links of the multi-root data processing system. Traffic of a particular priority group is routed from a single-root virtual hierarchy to a particular virtual link in the plurality of the virtual links based on the first mapping data structure and second mapping data structure.

Abstract: A computer-implemented method for a high speed peripheral component interconnect input/output virtualization configuration creates a set of virtual function path authorization tables, receives a request including a virtual function, from a requester, to provide requested data, and identifies a source address in the source system and a target address in each target system of the target set of systems. A virtual function work queue entry for the source system is created containing the source and the target address and responsive to determining the virtual function is authorized, write the requested data from the source address of the source system through a firewall of an intermediate device into the target address of each target system, wherein the intermediate device is one of a multi-root peripheral component interconnect device and a single root peripheral component interconnect device, and issuing a notice of completion to the requester.

Abstract: A computer-implemented method, apparatus, and computer program product are disclosed for routing error messages in a multiple host computer system environment to only those host computer systems that are affected by the error. The environment includes multiple host computer systems that share multiple devices utilizing a switched fabric. An error is detected in one of the devices. Routing tables that are stored in fabric devices in the fabric are used to identify ones of the host computer systems that are affected by the error. An error message that identifies the error is routed to only the identified ones of the host computer systems.

Abstract: Method, apparatus and system for isolating input/output adapter error domains in a data processing system. Errors occurring in one input/output adapter are isolated from other input/output adapters of the data processing system by functionality in a host bridge that connects the input/output adapters to a system bus of the data processing system, thus permitting the use of low cost, industry standard switches and bridges external to the host bridge.

Abstract: Mechanisms for migration stateless virtual functions from one virtual plane to another are provided. When a migration of a source virtual function to a destination virtual function in another virtual plane is to be performed, a source single root PCI manager (SR-PCIM) is first interrupted by a multiple root PCI manager (MR-PCIM). Configuration information that defines the source virtual function is then redefined on the destination virtual function for this stateless migration. A function level reset may then be performed on the source virtual function. The destination SR-PCIM may be interrupted by the MR-PCIM with an interrupt for the destination virtual function. A function level reset may then be performed on the destination virtual function. The destination virtual function state may then be changed to an “active” state such that the migrated virtual function begins processing transactions.

Abstract: Mechanisms for splitting responsibilities for communicating with an endpoint between a device driver and device driver services are provided. With these mechanisms, the device driver is responsible for managing queues for communicating requests between applications in a logical partition and the endpoint. The device driver further invokes memory management via device driver services. The device driver services are responsible for managing memory accessible by the endpoint, including the address translation and protection table (ATPT) or a root complex and the address translation caches (ATCs) of the endpoint. The device driver services may associate untranslated addresses for data structures used to communicate between a system image and the endpoint. The endpoint may request translations of the untranslated addresses and may cache the translations in the ATCs.

Abstract: A hypervisor, during device discovery, has code which can examine the south-side management data structure in an adapter's configuration space and determine the type of device which is being configured. The hypervisor may copy the south-side management data structure to a hardware management console (HMC) and the HMC can populate the data structure with south-side data and then pass the structure to the hypervisor to replace the data structure on the adapter. In another embodiment the hypervisor may copy the data structure to the HMC and the HMC can instruct the hypervisor to fill-in the data structure, a virtual function at a time, with south-side management data associations. The administrator can assign south-side data, such as a MAC address for a virtual instance of an Ethernet device, to LPARs sharing the adapter. Thus, a standard way to manage the south-side data of virtual functions is provided.

Abstract: Registering memory space for an application is performed. One or more open calls are received from an application to access one or more input/output (I/O) devices. Responsive to receiving the one or more open calls, one or more I/O map and pin calls are sent in order to register memory space for the one or more I/O devices within at least one storage area that will be accessed by the application. A verification is made as to whether the memory space to be registered is associated with the application. Responsive to the memory space being associated with the application, at least one virtual I/O bus address is received for each registered memory space of the one or more I/O devices. At least one I/O command is executed using the at least one virtual I/O bus address without intervention by an operating system or operating system image.

Abstract: Registering memory space within a data processing system is performed. One or more open calls are received from an application to access one or more input/output (I/O) devices. Responsive to receiving the one or more open calls, one or more I/O map and pin calls are sent in order to register memory space for the one or more I/O devices within at least one storage area that will be accessed by the application. At least one virtual I/O bus address is received for each registered memory space of the one or more I/O devices. At least one I/O command is executed using the at least one virtual I/O bus address without intervention by an operating system or operating system image.