Abstract: A bus bridge for use in a data processing system is disclosed in which the bridge includes a primary bus interface coupled to a primary bus, a secondary bus interface coupled to a secondary bus, a performance monitor register; and a state machine connected to the primary and secondary bus interfaces and configured to record the occurrence of a specified event in the performance monitor register. In a host bridge embodiment of the bridge, the primary bus is a host bus of the data processing system and the secondary bus is a PCI bus or PCI-X bus.

Abstract: A method and implementing system is provided in which multiple nodes of a Peripheral Component Interconnect PCI bridge/router circuit are connected to corresponding plurality of PCI busses to enable an extended number of PCI adapters to be connected within a computer system. Multiple enhanced arbiters are implemented to enable non-blocking and deadlock-free operation while still complying with PCI system requirements. An exemplary PCI-to-PCI router (PPR) circuit includes the arbiters as well as PPR buffers for temporarily storing transaction-related information passing through the router circuit between adapters on the PCI busses and/or between PCI adapters and the CPUs and system memory or other system devices. A buffer re-naming methodology is implemented to eliminate internal request/completion transaction information transfers between bridge buffers thereby increasing system performance.

Abstract: A method, data processing system, and I/O subsystem suitable for authorizing DMA accesses requested by a 64-bit I/O adapter are disclosed. The system includes one or more processors that have access to a system memory. A host bridge is connected between the processor(s) and an I/O bus. A first I/O adapter, which generates 32-bit addresses, is coupled to the host bridge. A second I/O adapter coupled to the host bridge is enabled to generate an address with a width greater than 32-bits (such as a 64-bit address). The system may include a Translation Control Entry (TCE) table, that is configured with information needed to translate an address generated by the 32-bit adapter to a wider address (such as a 64-bit address). In addition, the TCE may determine whether DMA access to the translated address by the requesting adapter is authorized. The system further includes an Access Control Table (ACT). The ACT determines whether DMA access to the address generated by the 64-bit I/O adapter is authorized.

Abstract: A method, system, and apparatus for isolating an input/output (I/O) bus error, received from an I/O adapter, from the other I/O adapters that may be in different partitions within a logically partitioned data process system is provided. In one embodiment, the logically partitioned data processing system includes a system bus, a processing unit, a memory unit, a host bridge, a plurality of terminal bridges, and a plurality of input/output adapters. The processing unit, memory unit, and the host bridge are all coupled to each other through the system bus. Each of the plurality of terminal bridges is coupled to the host bridge through a first bus. Each of the input/output adapters is coupled to one of the plurality of terminal bridges through a one of a plurality of second buses, such that each input/output adapter corresponds to a single terminal bridge. Each of the input/output adapters are assigned to one of a plurality of logical partitions within the data processing system.

Abstract: A method and implementing computer system are provided which enable a process for implementing a coherency system for bridge-cached data which is accessed by adapters and adapter bridge circuits which are normally outside of the system coherency domain. An extended architecture includes one or more host bridges. At least one of the host bridges is coupled to I/O adapter devices through a lower-level bus-to-bus bridge and one or more I/O busses. The host bridge maintains a buffer coherency directory and when Invalidate commands are received by the host bridge, the bridge buffers containing the referenced data are identified and the indicated data are invalidated.

Abstract: A computer system has physical pages of memory subject to access by input/output (“I/O”) devices, and a certain table with entries associating the physical pages with the I/O devices. Responsive to a request for data be moved from a first physical page to a second physical page, an entry is selected for the first physical page in the table. The selected entry indicates an association of the first physical page and one of the I/O devices. Arbitration is temporarily disabled for the selected I/O device so that I/O operations for the I/O device are temporarily disabled. Once arbitration is disabled for the device the data is moved from the first physical page to a second one of the physical pages and the entry is updated in the table to reflect a new association between the I/O device and the second physical page.

Abstract: A method, system, and apparatus for preventing input/output (I/O) adapters used by an operating system (OS) image, in a logically partitioned system, from accessing data from a memory location allocated to another OS image is provided. The system includes logical partitions, operating systems (OSs), memory locations, I/O adapters (IOAs), and a hypervisor. Each operating system image is assigned memory locations and input/output adapter is assigned to a logical partition. Each of the input/output adapters is assigned a range of I/O bus DMA addresses by the hypervisor. When a DMA operation request is received from an OS image, the hypervisor checks that the memory address range and the I/O adapter are allocated to the requesting OS image and that the I/O bus DMA range is within the that allocated to the I/O adapter. If these checks are passed, the hypervisor performs the requested mapping; otherwise the request is rejected.

Abstract: A PCI host bridge and an associated method of use are disclosed. The PCI host bridge includes a host bus interface, an I/O bus interface, and a PCI operation detection circuit. The host bus interface is suitable for communicating with a host bus of a data processing system and the I/O bus interface is suitable for communicating with a primary PCI bus operating in PCI-X mode. The PCI operation detection circuit is adapted to detect a PCI-X operation from the primary PCI bus that may have issued from a PCI mode adapter coupled to a secondary PCI bus. The detection circuit is further adapted to generate a modified operation for forwarding to the host bus in response to determining that the PCI-X operation may have originated from a PCI. mode adapter.

Abstract: A method and implementing computer system is provided in which specific device identification information is acquired when a faulty condition is detected during an information transfer transaction, and the condition is reported to the device driver of the identified device for corrective action without initiating a system shut-down. In one example, PCI adapter sequence information, including tag number, requester bus number, requester device number and requester function number is captured and used in reporting an error condition in order to identify and isolate the adapter in a recovery operation.

Abstract: An apparatus and method for implementing mulitcast in system area network channel adapters are provided. With the apparatus and method, a multicast packet is received in a channel adapter of an end node. The channel adapter determines which local queue pairs are party of the multicast group identified by a destination local identifier in the multicast data packet. Based on this determination, the channel adapter replicates the data packet and delivers a copy of the data packet to each local queue pair that is part of the multicast group.

Abstract: A method and apparatus is provided in which Pipelined Packet Transfers (PPT) are implemented. The PPT methodology includes a request phase and a response phase. The PPT request phase involves a PPT request master delivering to a PPT request target a source address, a destination address and an information packet for the interrupt being requested. The PPT response phase involves the PPT request target becoming a PPT response master with the PPT response master delivering to a PPT request master a destination address and a data packet which includes the interrupt processing information. Pipelined Packet transfers (PPT) are ordered in accordance with a predetermined processing priority to improve performance and avoid deadlock.

Abstract: A method and implementing system is provided in which multiple nodes of a PCI bridge/router circuit are connected to corresponding plurality of PCI busses to enable an extended number of PCI adapters to be connected within a computer system. Multiple enhanced arbiters are implemented to enable non-blocking and deadlock-free operation while still complying with PCI system requirements. An exemplary PCI-to-PCI router (PPR) circuit includes the arbiters as well as PPR buffers for temporarily storing transaction-related information passing through the router circuit between adapters on the PCI busses and/or between PCI adapters and the CPUs and system memory or other system devices. A buffer re-naming methodology is implemented to eliminate internal request/completion transaction information transfers between bridge buffers thereby increasing system performance.

Abstract: A method and implementing system are provided in which multiple nodes of a PCI bridge/router circuit are connected to corresponding plurality of PCI busses to enable an extended number of PCI adapters to be connected within a computer system. An exemplary PCI-to-PCI router (PPR) circuit includes the arbiters as well as PPR buffers for temporarily storing transaction-related information passing through the router circuit between adapters on the PCI busses and/or between PCI adapters and the CPUs and system memory or other system devices. A buffer re-naming methodology is implemented to eliminate internal request/completion transaction information transfers between bridge buffers thereby increasing system performance.

Abstract: A method and implementing system is provided in which system bridge circuits are enabled to execute, or over-commit to, transaction requests from system devices for information transfers which exceed the bridge circuit's current capacity to receive the requested information on its return from a designated target device such as system memory or another system device. The transaction request is moved along the data path to the designated target device and the requested information is returned, in an example, to the requesting device. By the time the requested information is returned to the requesting bridge circuit, a number of the holding buffers usually have been freed-up and are available to accept and pass the information to the requesting device.

Abstract: A method and implementing computer system are provided in which bridge buffers are grouped together in a pool, and are dynamically assigned and unassigned to adapter devices as needed during information transfers. In an exemplary peripheral component interconnect (PCI) system embodiment, a PCI Host Bridge (PHB) is coupled to a first PCI bus and one of the devices of the first PCI bus is occupied by a PCI-PCI bridge (PPB) which couples the first PCI bus to a second PCI bus. An assignment of PHB buffers in the PHB is made relative to the number of PCI devices which are connected both directly and indirectly to the first PCI bus. Devices on both the first and second PCI busses are given approximately equal status in the buffer assignment process. Upon a completion of a data transfer to or from any one of the adapters, the freed-up buffers which were assigned to that particular adapter are dynamically reassigned to other adapters as needed to optimize use of all of the buffers in the PHB pool.

Abstract: A method and apparatus is provided in which Pipelined Packet Transfers (PPT) are implemented. The PPT methodology includes a request phase and a response phase. The PPT request phase involves a PPT request master delivering to a PPT request target a source address, a destination address and an information packet for the interrupt being requested. The PPT response phase involves the PPT request target becoming a PPT response master with the PPT response master delivering to a PPT request master a destination address and a data packet which includes the interrupt processing information. Pipelined Packet transfers (PPT) are ordered in accordance with a predetermined processing priority to improve performance and avoid deadlock.

Abstract: A method and implementing system is provided in which multiple nodes of a PCI bridge/router circuit are connected to corresponding plurality of PCI busses to enable an extended number of PCI adapters to be connected within a computer system. Multiple enhanced arbiters are implemented to enable non-blocking and deadlock-free operation while still complying with PCI system requirements. An exemplary PCI-to-PCI router (PPR) circuit includes the arbiters as well as PPR buffers for temporarily storing transaction-related information passing through the router circuit between adapters on the PCI busses and/or between PCI adapters and the CPUs and system memory or other system devices. A buffer re-naming methodology is implemented to eliminate internal request/completion transaction information transfers between bridge buffers thereby increasing system performance.

Abstract: A method, system, and apparatus for processing foreign protocol requests, such as PCI transactions, across a system area network (SAN) utilizing a data packet protocol is provided while maintaining the other SAN traffic. In one embodiment, a HCA receives a request for a load or store operation from a processor to an I/O adapter using a protocol which is foreign to the system area network, such as a PCI bus protocol. The HCA encapsulates the request into a data packet and places appropriate headers and trailers in the data packet to ensure that the data packet is delivered across the SAN fabric to an appropriate TCA to which the requested I/O adapter is connected. The TCA receives the data packet, determines that it contains a foreign protocol request, and decodes the data packet to obtain the foreign protocol request. The foreign protocol request is then transmitted to the appropriate I/O adapter.

Abstract: A bus bridge with a pool of buffers sets including first and second buffer sets. The bridge includes steering logic for directing transactions issued by a first peripheral device to the first buffer set and transactions issued by the second peripheral device to the second buffer set. The bus bridge is configured to pull posted memory write transactions ahead of a delayed read completion transaction in the first buffer set in response to identifying the first peripheral device as a target of a read request issued by a processor. In one embodiment, the bus bridge is further configured to receive first and second device select signals from the first and second peripheral devices respectively. In this embodiment, the device select signals indicate the target of the read request issued by the processor.

Abstract: An apparatus and method for mediating a sequence of transactions across a fabric in a data processing system are implemented. A fabric bridge orders a preceding transaction and a subsequent transaction according to a predetermined protocol. Using the protocol a determination is made whether the subsequent transaction may be allowed to bypass the previous transaction, must be allowed to bypass the previous transaction, or must not be allowed to bypass the preceding transaction. Transactions include load/store (L/S) to system memory, and direct memory access (DMA) to system memory transactions.