Abstract: A semiconductor device includes a substrate having an active area, a first gate line extending along a first direction on the active area, a first gate line extension adjacent to the first gate line and outside the active area, a second gate line extending along the first direction on the active area and adjacent to the first gate line, and a second gate line extension adjacent to the second gate line and outside the active area. Preferably, the active area includes a first indentation and a second indentation, in which the first gate line extension overlaps the first indentation and the second gate line extension overlaps the first indentation.

Abstract: A semiconductor structure including chips is provided. The chips are arranged in a stack. Each of the chips includes a radio frequency (RF) device. Two adjacent chips are bonded to each other. The RF devices in the chips are connected in parallel. Each of the RF devices includes a gate, a source region, and a drain region. The gates in the RF devices connected in parallel have the same shape and the same size. The source regions in the RF devices connected in parallel have the same shape and the same size. The drain regions in the RF devices connected in parallel have the same shape and the same size.

Abstract: A method for fabricating a field-effect transistor includes the following steps. A gate structure layer in a line shape including a first region and a second region abutting to the first region is formed on a silicon layer. A first implanting process is performed to implant first-type dopants at least into a second portion of the second region of the gate structure layer. A second implanting region is performed to implant second-type dopants into the silicon layer to form a source region and a second region corresponding to the first region of the gate structure layer. The gate structure layer has a conductive-type junction at an interface between the first and second portions of the second region. A width of the silicon layer under the second region of the gate structure layer is smaller than a width of the gate structure layer.

Abstract: A structure of field-effect transistor includes a silicon layer of a silicon-on-insulator structure. A gate structure layer in a line shape is disposed on the silicon layer, wherein the gate structure layer includes a first region and a second region abutting to the first region. Trench isolation structures in the silicon layer are disposed at two sides of the gate structure layer, corresponding to the second region. The second region of the gate structure layer is disposed on the silicon layer and overlaps with the trench isolation structure. A source region and a drain region are disposed in the silicon layer at the two sides of the gate structure layer, corresponding to the first region. The second region of the gate structure layer includes a conductive-type junction portion.

Abstract: A semiconductor structure includes following components. A first substrate has a first surface and a second surface opposite to each other. An HBT device is located on the first substrate and includes a collector, a base, and an emitter. A first interconnect structure is electrically connected to the base, located on the first surface, and extends to the second surface. A second interconnect structure is electrically connected to the emitter, located on the first surface, and extends to the second surface. A third interconnect structure is located on the second surface and electrically connected to the collector. An MOS transistor device is located on a second substrate and includes a gate, a first source and drain region, and a second source and drain region. Interconnect structures on the second substrate electrically connect the base to the first source and drain region and electrically connect the emitter to the gate.

Abstract: A method for fabricating an inductor module includes steps of: providing a substrate; forming a first inter-level dielectric layer on the substrate; forming a plurality of second inter-level dielectric layers on the first inter-level dielectric layer; forming a trench penetrating at least two of the second inter-level dielectric layers; and forming a first metal layer in the trench.

Abstract: A varactor structure includes a substrate. A first and second gate structure are disposed on the substrate. The first and second gate structures each include a base portion and a plurality of line portions connected thereto. The line portions of each of the first and second gate structures is alternately arranged. A meander diffusion region is formed in the substrate and surrounds the line portions. A first set of contact plugs is planned with at least two columns or rows and disposed on the base portions of the first and second gate structures. A second set of contact plugs is planned with at least two columns or rows and disposed on the meander diffusion region. A first conductive layer is disposed on a top end of the first set of contact plugs. A second conductive layer is disposed on a top end of the second set of contact plugs.

Abstract: An inductor module and a method for fabricating the same are disclosed. The inductor module includes a substrate, a first inter-level dielectric layer, a plurality of second inter-level dielectric layers, a trench, and a first metal layer. The first inter-level dielectric layer is disposed on the substrate. The second inter-level dielectric layers are sequentially stacked on the first inter-level dielectric layer. The trench is disposed to penetrate at least two of the second inter-level dielectric layers. The first metal layer is disposed in the trench. The first metal layer has a top side surface and a bottom side surface opposite to each other. The top side surface is coplanar with an upper surface of the trench in the second inter-level dielectric layers. The bottom side surface is coplanar with a bottom surface of the trench in the second inter-level dielectric layers.

Abstract: A semiconductor structure including chips is provided. The chips are arranged in a stack. Each of the chips includes a radio frequency (RF) device. Two adjacent chips are bonded to each other. The RF devices in the chips are connected in parallel. Each of the RF devices includes a gate, a source region, and a drain region. The gates in the RF devices connected in parallel have the same shape and the same size. The source regions in the RF devices connected in parallel have the same shape and the same size. The drain regions in the RF devices connected in parallel have the same shape and the same size.

Abstract: A varactor structure includes a substrate. A first and second gate structure are disposed on the substrate. The first and second gate structures each include a base portion and a plurality of line portions connected thereto. The line portions of each of the first and second gate structures is alternately arranged. A meander diffusion region is formed in the substrate and surrounds the line portions. A first set of contact plugs is planned with at least two columns or rows and disposed on the base portions of the first and second gate structures. A second set of contact plugs is planned with at least two columns or rows and disposed on the meander diffusion region. A first conductive layer is disposed on a top end of the first set of contact plugs. A second conductive layer is disposed on a top end of the second set of contact plugs.

Abstract: A varactor structure includes a substrate. A first and second gate structure are disposed on the substrate. The first and second gate structures each include a base portion and a plurality of line portions connected thereto. The line portions of each of the first and second gate structures is alternately arranged. A meander diffusion region is formed in the substrate and surrounds the line portions. A first set of contact plugs is planned with at least two columns or rows and disposed on the base portions of the first and second gate structures. A second set of contact plugs is planned with at least two columns or rows and disposed on the meander diffusion region. A first conductive layer is disposed on a top end of the first set of contact plugs. A second conductive layer is disposed on a top end of the second set of contact plugs.

Abstract: An SOI semiconductor device includes a substrate, a buried oxide layer disposed on the substrate, a top semiconductor layer disposed on the buried oxide layer, a source doping region and a drain doping region in the top semiconductor layer, a channel region between the source doping region and the drain doping region in the top semiconductor layer, a gate electrode on the channel region, and an embedded doping region disposed in the top semiconductor layer and directly under the channel region. The embedded doping region acts as a hole sink to alleviate or avoid floating body effects.

Abstract: The invention provides a seal ring structure, which comprises a substrate, and a seal ring positioned on the substrate, wherein the seal ring comprises an inner seal ring comprising a plurality of inner seal units, wherein each of the inner seal units is arranged at intervals with each other, an outer seal ring comprising a plurality of outer seal units arranged at the periphery of the inner seal ring, wherein each of the outer seal units is arranged at intervals with each other, and a plurality of groups of fence-shaped seal units, wherein at least one group of fence-shaped seal units is positioned between one of the inner seal units and the other adjacent outer seal unit.

Abstract: A bonded semiconductor structure includes a first device wafer and a second device wafer. The first device wafer includes a first insulating layer, a first device layer on the first insulating layer, and a first bonding layer on the first device layer. The second device wafer includes a second insulating layer, a second device layer on a first side of the second insulating layer, and a second bonding layer on the second device layer. The second device layer includes a second device region and a second transistor in the second device region. The second device wafer is bonded to the first device wafer by bonding the second bonding layer with the first bonding layer. A shielding structure is on a second side of the second insulating layer opposite to the first side and vertically overlapped with the second device region.

Abstract: A structure of field-effect transistor includes a silicon layer of a silicon-on-insulator structure. A gate structure layer in a line shape is disposed on the silicon layer, wherein the gate structure layer includes a first region and a second region abutting to the first region. Trench isolation structures in the silicon layer are disposed at two sides of the gate structure layer, corresponding to the second region. The second region of the gate structure layer is disposed on the silicon layer and overlaps with the trench isolation structure. A source region and a drain region are disposed in the silicon layer at the two sides of the gate structure layer, corresponding to the first region. The second region of the gate structure layer includes a conductive-type junction portion.

Abstract: A structure of field-effect transistor includes a silicon layer of a silicon-on-insulator structure. A gate structure layer in a line shape is disposed on the silicon layer, wherein the gate structure layer includes a first region and a second region abutting to the first region. Trench isolation structures in the silicon layer are disposed at two sides of the gate structure layer, corresponding to the second region. The second region of the gate structure layer is disposed on the silicon layer and overlaps with the trench isolation structure. A source region and a drain region are disposed in the silicon layer at the two sides of the gate structure layer, corresponding to the first region. The second region of the gate structure layer includes a conductive-type junction portion.

Abstract: A structure of field-effect transistor includes a silicon layer of a silicon-on-insulator structure. A gate structure layer in a line shape is disposed on the silicon layer, wherein the gate structure layer includes a first region and a second region abutting to the first region. Trench isolation structures in the silicon layer are disposed at two sides of the gate structure layer, corresponding to the second region. The second region of the gate structure layer is disposed on the silicon layer and overlaps with the trench isolation structure. A source region and a drain region are disposed in the silicon layer at the two sides of the gate structure layer, corresponding to the first region. The second region of the gate structure layer includes a conductive-type junction portion.

Abstract: An inductor module and a method for fabricating the same are disclosed. The inductor module includes a substrate, a first inter-level dielectric layer, a plurality of second inter-level dielectric layers, a trench, and a first metal layer. The first inter-level dielectric layer is disposed on the substrate. The second inter-level dielectric layers are sequentially stacked on the first inter-level dielectric layer. The trench is disposed to penetrate at least two of the second inter-level dielectric layers. The first metal layer is disposed in the trench. The first metal layer has a top side surface and a bottom side surface opposite to each other. The top side surface is coplanar with an upper surface of the trench in the second inter-level dielectric layers. The bottom side surface is coplanar with a bottom surface of the trench in the second inter-level dielectric layers.

Abstract: The invention provides a seal ring structure, which comprises a substrate, and a seal ring positioned on the substrate, wherein the seal ring comprises an inner seal ring comprising a plurality of inner seal units, wherein each of the inner seal units is arranged at intervals with each other, an outer seal ring comprising a plurality of outer seal units arranged at the periphery of the inner seal ring, wherein each of the outer seal units is arranged at intervals with each other, and a plurality of groups of fence-shaped seal units, wherein at least one group of fence-shaped seal units is positioned between one of the inner seal units and the other adjacent outer seal unit.

Abstract: A structure of field-effect transistor includes a silicon layer of a silicon-on-insulator structure. A gate structure layer in a line shape is disposed on the silicon layer, wherein the gate structure layer includes a first region and a second region abutting to the first region. Trench isolation structures in the silicon layer are disposed at two sides of the gate structure layer, corresponding to the second region. The second region of the gate structure layer is disposed on the silicon layer and overlaps with the trench isolation structure. A source region and a drain region are disposed in the silicon layer at the two sides of the gate structure layer, corresponding to the first region. The second region of the gate structure layer includes a conductive-type junction portion.