Abstract: An apparatus relates generally to a clock generator is disclosed. The clock generator is coupled to receive an input clock signal and further coupled to provide an output clock signal. An address and control register is coupled to receive an address signal and the output clock signal. An access generator is coupled to receive the output clock signal. The clock generator includes: an input node coupled to receive the input clock signal; at least one pulse generator coupled to the input node to receive the input clock signal and further coupled to provide a clock control signal; and a control gate coupled to the input node to receive the input signal and further coupled to the at least one pulse generator to receive the clock control signal. The clock control signal is provided in a non-toggling state for a high-frequency mode and in a toggling state for a low-frequency mode.

Abstract: An integrated circuit and method for using a synchronous reset pulse to reset a circuitry comprising a plurality of clock domains are disclosed. For example, the method of the present disclosure provides a reset signal that is synched to one clock, takes the synchronous signal and resets circuits in a plurality of clock domains. In order to reset a portion of the circuit which is in a particular clock domain, the reset needs to be synchronized to the clock of the particular domain.

Abstract: A non-transitory storage medium stores an assembled genetic sequence comprising aligned sequencing reads. An electronic processing device is configured to perform operations including: identifying a possible variant in the assembled genetic sequence; computing value of at least one read property for reads of the assembled genetic sequence; and calling the possible variant conditional upon the computed values of the at least one read property for sequencing reads of the assembled genetic sequence that include the possible variant satisfying an acceptance criterion. The electronic processing device may be further configured to select at least one region of the assembled genetic sequence for validation based on a non random selection criterion.

Abstract: A circuit can include address evaluation circuitry coupled to an address bus of a memory and configured to generate a first control signal responsive to determining that an address on the address bus has not changed for a current clock cycle from a previous clock cycle. The circuit can include write enable evaluation circuitry coupled to the memory and configured to generate a second control signal responsive to determining that a write enable signal of the memory is de-asserted for the current clock cycle and for the previous clock cycle. The circuit can include clock enable circuitry coupled to a clock enable port of the memory and configured to generate a clock enable signal to the clock enable port of the memory responsive to the first control signal and the second control signal.

Abstract: An example network management device includes a network management module, and a reconstruction module. The network management module is configured to generate a data retrieval command to direct a managed device to retrieve a set of management variables stored within a database within the managed network device and send the data retrieval command to the managed device. The reconstruction module is configured to receive a plurality of partial responses generated by a deconstruction module of the managed device in response to receiving the data retrieval command and determining that the set of management variables does not fit in a single response, and combine the received plurality of partial responses into the requested set of management variables, wherein each of the plurality of partial responses is received as a separate message from the managed network device and includes a different portion of the requested set of management variables.

Abstract: An application integration system used to integrate a plurality of applications includes a plurality of integration adapters, each communicating with an application and an integration engine including a messaging broker, an integration database and a schema mapping. database. The application integration system also uses a plurality of tools and components interactively working with the messaging broker. The application integration system allows integrating various applications and at the same time provides ease of change to users of such applications by providing a framework that may be used to customize and configure integrations leading to significant reduction in total cost of ownership to the businesses.

Abstract: A data value is read from one port of a dual-port memory cell during a clock cycle. A WRITE assist pulse having a delay from an end-of-read signal is generated. The delay and duration of the WRITE assist pulse are optionally user-selectable. A high voltage (e.g., Vdd) is coupled to the bitlines (e.g., BL-A, BLc-A) of the first port during the WRITE assist pulse, and a low voltage value (e.g., zero) is written to the memory cell through the second port (e.g., BL-B, BLc-B) during the clock cycle.

Abstract: A composition is described, comprising: (a) from 20 to 80 wt % of a polyester; (b) from 5 to 35 wt % of a flame retardant phosphinate of the formula (I) [(R1)(R2)(PO)—O]?mMm+??(I), a flame retardant diphosphinate of the formula (II) [(O—POR1)(R3)(POR2—O)]2?nMxm+??(II), and/or a flame retardant polymer derived from the flame retardant phosphinate of the formula (I) or the flame retardant diphosphinate of the formula (II), wherein R1 and R2 are identical or different and are H, C1-C6-alkyl, linear or branched, or C6-C10-aryl; R3 is C1-C10-alkylene, linear or branched, C6-C10-arylene, -alkylarylene or -arylalkylene; M is an alkaline earth metal, alkali metal, Al, Ti, Zn, Fe, or boron; m is 1, 2, 3 or 4; n is 1, 2, or 3; and x is 1 or 2; (c) from 1 to 25 wt % of a melamine polyphosphate, melamine cyanurate, melamine pyrophosphate, and/or melamine phosphate; (d) from more than 0 to 25 wt % of a polyetherimide; and (e) optionally, an additive.

Abstract: A system and method for dividing three-dimensional patches into tasks for processing receives control points defining a three dimensional patch and determines if a number of vertices of the three dimensional patch is greater than a maximum value. When the number of vertices is not greater than the maximum value, the three dimensional patch is output as a single task. When the number of vertices is greater than the maximum value, the three dimensional patch is divided into multiple tasks that each include a number of vertices that is not greater than the maximum value and the multiple tasks are output.

Abstract: A computer-implemented method of identifying timing paths of a circuit block can include representing a circuit block including at least one bypassable component as a block diagram having a plurality of elements linked by nodes. The method can include generating a map file including a text description of each element within the block diagram, wherein the text description of each element specifies a bypass indicator for the element. The method also can include generating a plurality of sub-paths from the map file, determining timing paths from the plurality of sub-paths by selectively combining different ones of the plurality of sub-paths according to commonality of starting points and ending points of the plurality of sub-paths, and outputting the timing paths.

Abstract: A circuit for repairing defective memory of an integrated circuit is disclosed. The circuit includes blocks of memory; and interconnect elements providing data to each of the blocks of memory, where the interconnect elements enable coupling together the signals for programming the blocks of memory. The circuit also includes a directory of locations for defective memory cells of blocks of memory, where the directory of locations is common to the blocks of memory for storing locations of defective memory cells of the blocks of memory. Methods of repairing defective memory of an integrated circuit are also disclosed.

Abstract: A system, method, and computer program product are provided for validating a graphics processor design. In operation, a test image is identified. Additionally, a reference image is automatically selected from a set of reference images. Furthermore, a graphics processor design is validated using the test image and the selected reference image.

Abstract: A composition comprises 20 to 80 wt. % of a polyester component comprising a modified polybutylene terephthalate random copolymer derived from a polyethylene terephthalate component selected from polyethylene terephthalate and polyethylene terephthalate copolymers and having at least one residue derived from the polyethylene terephthalate component; from 5 to 35 wt. % of a flame retardant phosphinate (I) or (II) (R1)(R2)(PO)—O]?mMm+??(I) [(O—POR1)(R3)(POR2—O)]2?nMm+x??(II), and/or a flame retardant polymer thereof, wherein R1 and R2 are independently are H, C1-C6-alkyl, or C6-C10-aryl; R3 is C1-C10, alkylene, C6-C10-arylene, -alkylarylene or -arylalkylene; M is an alkaline earth metal, alkali metal, Al, Ti, Zn, Fe, or boron; m is 1, 2, 3 or 4; n is 1, 2, or 3; and x is 1 or 2; 1 to 25 wt. % of a melamine polyphosphate, melamine cyanurate, melamine pyrophosphate, and/or melamine phosphate; and more than 0 to 25 wt. % of a polyetherimide.

Abstract: A system (10) for executing an application (30) on a computer (40) where the application (30) is stored on a portable re-writable storage device (15), the system (10) comprising: a configuration file (25) in a backup location (24) on the device (15), the configuration file (25) containing information to enable an application (30) stored on the device (15) to be executed by the computer (40), an application manager (20) to compare stored configuration files (25) on the device (15) to identify a corresponding configuration file (25) for the application (30) stored on the device (15) to be executed by the computer (40), and to read the corresponding configuration file (25) to cause the computer (40) to recognise that the application (30) was installed on the computer (40) to permit the application (30) to be executed by the computer (40).

Abstract: Duplicate record processing is enabled employing on customizable rules. Detected duplicate records are merged, deleted, deactivated, or moved based on one or more sets of customizable rules. Different rule sets may be used for each record type, or a rule set reused for different records. Hierarchical relationships between master and child records are adjusted upon duplicate processing based on rules and/or record attributes.

Abstract: A composition is described, comprising: (a) from 20 to 80 wt % of a polyester; (b) from 5 to 35 wt % of a flame retardant phosphinate of the formula (I) [(R1)(R2)(PO)—O]?mMm+??(I), a flame retardant diphosphinate of the formula (II) [(O—POR1)(R3)(POR2—O)]2?nMxm+??(II), and/or a flame retardant polymer derived from the flame retardant phosphinate of the formula (I) or the flame retardant diphosphinate of the formula (II), wherein R1 and R2 are identical or different and are H, C1-C6-alkyl, linear or branched, or C6-C10-aryl; R3 is C1-C10-alkylene, linear or branched, C6-C10-arylene, -alkylarylene or -arylalkylene; M is an alkaline earth metal, alkali metal, Al, Ti, Zn, Fe, or boron; m is 1, 2, 3 or 4; n is 1, 2, or 3; and x is 1 or 2; (c) from 1 to 25 wt % of a melamine polyphosphate, melamine cyanurate, melamine pyrophosphate, and/or melamine phosphate; (d) from more than 0 to 25 wt % of a polyetherimide; and (e) optionally, an additive.

Abstract: Duplicate record processing is enabled employing on customizable rules. Detected duplicate records are merged, deleted, deactivated, or moved based on one or more sets of customizable rules. Different rule sets may be used for each record type, or a rule set reused for different records. Hierarchical relationships between master and child records are adjusted upon duplicate processing based on rules and/or record attributes.

Abstract: A composition of matter comprising a polyester composition derived from: (i) 20 to 80 mole percent of a first diol derived from a disubstituted xylene glycol of the formula (I): wherein R1 and R2 are independently selected from the group consisting of aliphatic radical, aromatic radical, cycloaliphatic, radical and halogen; and (ii) a second diol and (iii) a diacid is disclosed. Also disclosed are blends of these polyesters with polycarbonate and process to prepare these compositions and articles therefrom.

Abstract: A composition of matter comprising a polyester composition derived from: (i) greater than 80 mole percent of a diol derived from a disubstituted xylene glycol of the formula (I): wherein R1 and R2 are independently selected from the group consisting of aliphatic, aromatic, cycloaliphatic, sulfur containing compounds, amines and halogen; and (ii) a diacid is disclosed. Also disclosed are blends of these polyesters with polycarbonate and process to prepare these compositions and articles therefrom.

Abstract: A solid state magnetic memory system and method disposes an array of magnetic media cells in an array on a substrate. In an exemplary embodiment, drive electronics are fabricated into the substrate through conventional CMOS processing in alignment with associated cells of the array. The magnetic media cells each include a magnetic media bit and a magnetoresistive or GMR stack for reading the state of the media bit. Addressing lines are juxtaposed with the media bits to permit programming and erasing of selected ones of the bits. In at least some embodiments, sector erase may be performed.