Patents by Inventor Sudeep Mandal
Sudeep Mandal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11782181Abstract: A downhole multi-modality inspection system includes a first imaging device operable to generate first imaging data and a second imaging device operable to generate second imaging data. The first imaging device includes a first source operable to emit energy of a first modality, and a first detector operable to detect returning energy induced by the emitted energy of the first modality. The second imaging device includes a second source operable to emit energy of a second modality, and a second detector operable to detect returning energy induced by the emitted energy of the second modality. The system further includes a processor configured to receive the first imaging data and the second imaging data, and integrate the first imaging data with the second imaging data into an enhanced data stream. The processor correlates the first imaging data and the second imaging data to provide enhanced data for detecting potential wellbore anomalies.Type: GrantFiled: August 13, 2018Date of Patent: October 10, 2023Assignee: GE Energy Oilfield Technology, Inc.Inventors: Ansas Matthias Kasten, Yuri Plotnikov, Sudeep Mandal, Sarah Lillian Katz, Frederick Wheeler, William Robert Ross, John Scott Price
-
Publication number: 20200132975Abstract: A microscope is provided. The microscope includes an illumination source configured to provide illumination beams to image a portion of a biological sample. The microscope also includes an optical unit configured to enable both phase contrast imaging and multicolor fluorescence imaging of the portion of the biological sample utilizing parallel point scanning. The microscope further includes a detector configured to simultaneously acquire multiple point images at different locations of the portion of the biological sample.Type: ApplicationFiled: October 26, 2018Publication date: April 30, 2020Inventors: Ansas Matthias Kasten, William Albert Challener, Jason Harris Karp, Sudeep Mandal
-
Patent number: 10634890Abstract: A microscope is provided. The microscope includes an illumination source configured to provide illumination beams to image a portion of a biological sample. The microscope also includes an optical unit configured to enable both phase contrast imaging and multicolor fluorescence imaging of the portion of the biological sample utilizing parallel point scanning. The microscope further includes a detector configured to simultaneously acquire multiple point images at different locations of the portion of the biological sample.Type: GrantFiled: October 26, 2018Date of Patent: April 28, 2020Assignee: GENERAL ELECTRIC COMPANYInventors: Ansas Matthias Kasten, William Albert Challener, Jason Harris Karp, Sudeep Mandal
-
Patent number: 10400574Abstract: An apparatus for inspecting integrity of a multi-barrier wellbore is described. The apparatus includes at least one source to generate radiation to impinge a target volume of the wellbore. The apparatus includes a source collimator having a plurality of alternating blocking channels and passing channels to direct radiation to impinge the target volume, such that the radiation directed from each passing channel forms a plurality of field of views extending radially into the target volume. The apparatus further includes at least one detector to receive backscatter rays arising from each respective field of view from the plurality of field of views and to generate an image representative of an inspected portion of the wellbore. The apparatus is useful for inspecting very small volumes in the multiple barriers of the wellbore and determine the integrity of the wellbore based on the different densities in the image of the inspected portion.Type: GrantFiled: August 28, 2017Date of Patent: September 3, 2019Assignee: General Electric CompanyInventors: Ansas Matthias Kasten, Juan Pablo Cilia, John Scott Price, William Robert Ross, Chengbao Wang, Sudeep Mandal
-
Patent number: 10393532Abstract: In an approach for determining navigation routes, a computer identifies an emergency situation and a corresponding location. The computer identifies an emergency service based on the identified emergency situation and the corresponding location. The computer identifies an emergency treatment provider based on the identified emergency situation and the corresponding location. The computer determines a navigation route based on respective locations of the identified emergency situation, the identified emergency service, and the identified emergency treatment provider. The computer identifies one or more incoming devices on the determined navigation route. The computer determines an alternate navigation route for the identified one or more incoming devices, wherein the determined alternate navigation route reduces travel on the determined navigation route.Type: GrantFiled: October 20, 2015Date of Patent: August 27, 2019Assignee: International Business Machines CorporationInventors: Eric A. Foreman, Sudeep Mandal
-
Patent number: 10304763Abstract: A method for producing wafer level packaging using an embedded leadframe strip and the resulting device are provided. Embodiments include placing dies into a mold with an active side of each die facing a surface of the mold; placing a leadframe strip on the mold, wherein the leadframe strip includes etched and half etched portions positioned between each die; placing a mold cover over the mold and dies; and adding mold compound in spaces between the dies and mold cover.Type: GrantFiled: December 29, 2017Date of Patent: May 28, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Richard S. Graf, Sudeep Mandal, Kibby Horsford
-
Patent number: 10249590Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to stacked dies using one or more interposers and methods of manufacture. The structure includes: at least one die comprising a plurality of via interconnects, the plurality of via interconnects comprising at least one functional via interconnect, one defective via interconnect and one redundant functional via interconnect to compensate for the one defective via interconnect; and an interposer which includes interconnects that aligns to and electrically connects the at least one functional via interconnect and the redundant functional via interconnect of different dies when the interposer is oriented in a predetermined orientation.Type: GrantFiled: June 6, 2017Date of Patent: April 2, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Sudeep Mandal, Sebastian T. Ventrone, Richard S. Graf
-
Publication number: 20190063208Abstract: An apparatus for inspecting integrity of a multi-barrier wellbore is described. The apparatus includes at least one source to generate radiation to impinge a target volume of the wellbore. The apparatus includes a source collimator having a plurality of alternating blocking channels and passing channels to direct radiation to impinge the target volume, such that the radiation directed from each passing channel forms a plurality of field of views extending radially into the target volume. The apparatus further includes at least one detector to receive backscatter rays arising from each respective field of view from the plurality of field of views and to generate an image representative of an inspected portion of the wellbore. The apparatus is useful for inspecting very small volumes in the multiple barriers of the wellbore and determine the integrity of the wellbore based on the different densities in the image of the inspected portion.Type: ApplicationFiled: August 28, 2017Publication date: February 28, 2019Inventors: Ansas Matthias Kasten, Juan Pablo Cilia, John Scott Price, William Robert Ross, Chengbao Wang, Sudeep Mandal
-
Patent number: 10208587Abstract: A detector assembly includes scintillators configured to generate a light signal in response to an impinging backscatter signal, where the scintillators are arranged in a first pattern, a plurality of first detectors, where each first detector is coupled to a scintillator and configured to receive a first portion of a light signal from that scintillator, and where the first detectors are arranged in a second pattern aligned with the first pattern, a plurality of second detectors, where each second detector is disposed adjacent a scintillator and configured to receive a second portion of the light signal from that scintillator, and where the plurality of second detectors is arranged in a third pattern, and a scintillator collimator including a plurality of openings and configured to selectively receive the backscatter signal, where the detector assembly is configured to provide depth resolution, azimuthal resolution, a defect type, a defect size, or combinations thereof.Type: GrantFiled: August 28, 2017Date of Patent: February 19, 2019Assignee: General Electric CompanyInventors: Ansas Matthias Kasten, John Scott Price, Juan Pablo Cilia, Chengbao Wang, William Robert Ross, Brian David Yanoff, Stanislav Ivanovich Soloviev, Sudeep Mandal
-
Publication number: 20190049622Abstract: A downhole multi-modality inspection system includes a first imaging device operable to generate first imaging data and a second imaging device operable to generate second imaging data. The first imaging device includes a first source operable to emit energy of a first modality, and a first detector operable to detect returning energy induced by the emitted energy of the first modality. The second imaging device includes a second source operable to emit energy of a second modality, and a second detector operable to detect returning energy induced by the emitted energy of the second modality. The system further includes a processor configured to receive the first imaging data and the second imaging data, and integrate the first imaging data with the second imaging data into an enhanced data stream. The processor correlates the first imaging data and the second imaging data to provide enhanced data for detecting potential wellbore anomalies.Type: ApplicationFiled: August 13, 2018Publication date: February 14, 2019Applicant: GE Energy Oilfield Technology, Inc.Inventors: Ansas Matthias Kasten, Yuri Plotnikov, Sudeep Mandal, Sarah Lillian Katz, Frederick Wheeler, William Robert Ross, John Scott Price
-
Patent number: 10170224Abstract: A structure and method for fabricating a laterally configured thin film varistor surge protection device using low temperature sputtering techniques which do not damage IC device components contiguous to the varistor being fabricated. The lateral thin film varistor may include a continuous layer of alternating regions of a first metal oxide layer and a second metal oxide layer formed between two laterally spaced electrodes using a low temperature sputtering process followed by a low temperature annealing process.Type: GrantFiled: November 22, 2017Date of Patent: January 1, 2019Assignee: International Business Machines CorporationInventors: Jeffrey P. Gambino, Richard S. Graf, Sudeep Mandal
-
Publication number: 20180350684Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to stacked dies using one or more interposers and methods of manufacture. The structure includes: at least one die comprising a plurality of via interconnects, the plurality of via interconnects comprising at least one functional via interconnect, one defective via interconnect and one redundant functional via interconnect to compensate for the one defective via interconnect; and an interposer which includes interconnects that aligns to and electrically connects the at least one functional via interconnect and the redundant functional via interconnect of different dies when the interposer is oriented in a predetermined orientation.Type: ApplicationFiled: June 6, 2017Publication date: December 6, 2018Inventors: SUDEEP MANDAL, SEBASTIAN T. VENTRONE, RICHARD S. GRAF
-
Patent number: 10120102Abstract: A fluid sensor cable assembly and method uses one or more conductive bodies extending along an elongated core body for conducting a heating current to heat the cable assembly. The one or more conductive bodies also are configured to conduct an interrogation signal and to conduct reflections of the interrogation signal. One or more optical fibers extend along the length of the core body and include temperature sensitive elements at different locations along the length of the core body. The temperature sensitive elements measure heat flux out of the cable assembly at the different locations subsequent to heating the cable assembly and communicate the heat flux to a computer acquisition system.Type: GrantFiled: November 4, 2015Date of Patent: November 6, 2018Assignee: General Electric CompanyInventors: Loucas Tsakalakos, Slawomir Rubinsztajn, Renato Guida, Mahadevan Balasubramaniam, Boon Kwee Lee, Brian Magann Rush, Faisal Razi Ahmad, Sudeep Mandal, David Sirda Shanks
-
Patent number: 10049570Abstract: Various embodiments include approaches for analyzing a set of travel pathways for a priority vehicle. In some cases, an approach includes: obtaining data indicating a location of the priority vehicle and a location of a destination for the priority vehicle; ranking each of a set of paths between the location of the priority vehicle and the location of the destination based upon a travel time for the priority vehicle along the set of paths; and sending instructions to vehicles on a highest-ranked path in the set of paths to initiate providing a right-of-way to the priority vehicle, wherein vehicles closer to the destination along the highest-ranked path are instructed to change a corresponding position prior to vehicles farther from the destination along the highest-ranked path.Type: GrantFiled: October 21, 2015Date of Patent: August 14, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Eric A. Foreman, Sudeep Mandal
-
Patent number: 10043962Abstract: Structures that include thermoelectric couples and methods for fabricating such structures. A device level and a back-end-of-line (BEOL) interconnect structure are fabricated at a front side of a substrate. A thermoelectric couple is formed that is coupled with the substrate. The thermoelectric couple includes a first through-silicon via extending through the device level and the substrate to a back side of the substrate, a second through-silicon via extending through the device level and the substrate to the back side of the substrate, an n-type thermoelectric pillar coupled with the first through-silicon via, and a p-type thermoelectric pillar coupled with the second through-silicon via. The BEOL interconnect structure includes a wire that couples the first through-silicon via in series with the second through-silicon via.Type: GrantFiled: May 5, 2016Date of Patent: August 7, 2018Assignee: GLOBALFOUNDRIES Inc.Inventors: Sudeep Mandal, Richard S. Graf
-
Patent number: 10013519Abstract: Various embodiments include approaches for designing three-dimensional (3D) integrated circuits (ICs). In one embodiment, a system is configured to: read an electronic chip identification (ECID) for a plurality of dies formed from distinct wafer lots, the ECID indicating a process performance parameter for each distinct wafer lot; create a reference table mapping a back-bias voltage to be applied to each die to the process performance parameter for each distinct wafer lot; determine performance requirements of a customer design for the 3D IC structure; assemble the design of the 3D IC structure including a set of dies selected from at least two of the distinct wafer lots; and assign a back bias voltage to each die based upon the performance requirements of the customer design and the reference table.Type: GrantFiled: September 20, 2016Date of Patent: July 3, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Sudeep Mandal, Jeanne P. Bickford
-
Publication number: 20180122730Abstract: A method for producing wafer level packaging using an embedded leadframe strip and the resulting device are provided. Embodiments include placing dies into a mold with an active side of each die facing a surface of the mold; placing a leadframe strip on the mold, wherein the leadframe strip includes etched and half etched portions positioned between each die; placing a mold cover over the mold and dies; and adding mold compound in spaces between the dies and mold cover.Type: ApplicationFiled: December 29, 2017Publication date: May 3, 2018Inventors: Richard S. GRAF, Sudeep MANDAL, Kibby HORSFORD
-
Patent number: 9952500Abstract: Embodiments of the present disclosure include methods, program products, and systems for adjusting an integrated circuit (IC) layout for optical proximity correction (OPC). Methods according to the disclosure can include: defining a target region of the IC design layout, the target region having a plurality of patterns including a first pattern positioned adjacent to a second pattern, wherein an OPC modeling rule of the IC design layout prohibits the first pattern from being adjusted, and wherein the second pattern does not reduce a printability metric of the first pattern; adjusting the design of the second pattern to reduce at least one printing error in the first pattern, wherein a functionality of the second pattern in the IC design layout is unchanged after the adjusting; and implementing OPC on the IC design layout including the target region with the adjusted second pattern therein.Type: GrantFiled: August 17, 2016Date of Patent: April 24, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Sudeep Mandal, Arun S. Mampazhy
-
Patent number: 9941458Abstract: A semiconductor device package and method for manufacturing the same, includes a semiconductor substrate including a plurality of embedded thermoelectric couples. The embedded thermoelectric couples can be in trenches and extend partially into the substrate from the handle side of the substrate. An n-type pillar and a p-type pillar are electrically connected using a conducting contact plate to form each of the partially embedded thermoelectric couples. A series connection layer electrically connects the plurality of thermoelectric couples on the handle side. A power source provides electrical current to the series connection layer allowing current to flow through the plurality of the series connected thermoelectric couples. A heat sink is positioned adjacent to the connected thermoelectric couples for transferring heat away from the device side to the heat sink using the thermoelectric couples.Type: GrantFiled: September 11, 2015Date of Patent: April 10, 2018Assignee: International Business Machines CorporationInventors: Jeffrey P. Gambino, Richard S. Graf, Sudeep Mandal
-
Publication number: 20180096760Abstract: A structure and method for fabricating a laterally configured thin film varistor surge protection device using low temperature sputtering techniques which do not damage IC device components contiguous to the varistor being fabricated. The lateral thin film varistor may include a continuous layer of alternating regions of a first metal oxide layer and a second metal oxide layer formed between two laterally spaced electrodes using a low temperature sputtering process followed by a low temperature annealing process.Type: ApplicationFiled: November 22, 2017Publication date: April 5, 2018Inventors: Jeffrey P. Gambino, Richard S. Graf, Sudeep Mandal