Abstract: A structure and method for fabricating a laterally configured thin film varistor surge protection device using low temperature sputtering techniques which do not damage IC device components contiguous to the varistor being fabricated. The lateral thin film varistor may consist of a continuous layer of alternating regions of a first metal oxide layer and a second metal oxide layer formed between two laterally spaced electrodes using a low temperature sputtering process followed by a low temperature annealing process.

Abstract: An integrated conductive polymer-solder ball structure is provided. The integrated conductive polymer-solder ball structure comprises a sputter seed layer applied to a wafer structure, one or more conductive polymer pad structures applied to the sputtered seed layer at locations on the wafer structure where one or more solder ball structures will be formed, an electroplating layer applied to portions of the one or more conductive polymer pad structures where a photoresist layer has been exposed, and a solder ball formed on each of the electroplating layers thereby forming the one or more solder ball structures.

Abstract: A chip fabricated from a semiconductor material is disclosed, which may include active devices located below a first depth from the chip back side, and a structure to remove heat from the active devices to the chip back side. The structure may include thermally conductive partial vias (TCPVs), which may include a recess with a depth, from the chip back side towards the active devices less than the first depth. Each TCPV may include a barrier layer deposited within the recess and deposited upon the back side of the chip. Each TCPV may also include a thermally conductive layer deposited upon the barrier layer. The structure may also include through-silicon vias (TSVs) electrically connected to active devices, extending from the back side to an active device side of the chip to conductively remove heat from the active devices to the back side of the chip.

Abstract: A semiconductor device package and method for manufacturing the same, includes a semiconductor substrate including a plurality of embedded thermoelectric couples. The embedded thermoelectric couples can be in trenches and extend partially into the substrate from the handle side of the substrate. An n-type pillar and a p-type pillar are electrically connected using a conducting contact plate to form each of the partially embedded thermoelectric couples. A series connection layer electrically connects the plurality of thermoelectric couples on the handle side. A power source provides electrical current to the series connection layer allowing current to flow through the plurality of the series connected thermoelectric couples. A heat sink is positioned adjacent to the connected thermoelectric couples for transferring heat away from the device side to the heat sink using the thermoelectric couples.

Abstract: A semiconductor device package and method for manufacturing the same, includes a semiconductor substrate including a plurality of embedded thermoelectric couples. The embedded thermoelectric couples can be in trenches and extend partially into the substrate from the handle side of the substrate. An n-type pillar and a p-type pillar are electrically connected using a conducting contact plate to form each of the partially embedded thermoelectric couples. A series connection layer electrically connects the plurality of thermoelectric couples on the handle side. A power source provides electrical current to the series connection layer allowing current to flow through the plurality of the series connected thermoelectric couples. A heat sink is positioned adjacent to the connected thermoelectric couples for transferring heat away from the device side to the heat sink using the thermoelectric couples.

Abstract: The present invention relates generally to integrated circuit (IC) chip packaging, and more particularly, to a structure and method of forming a glass interposer having one or more embedded peltier devices, alongside electrically conductive vias, to help dissipate heat from one or more IC chips in a multi-dimensional chip package through the glass interposer and into an organic carrier, where it can be dissipated into an underlying substrate.

Abstract: The present invention relates generally to integrated circuit (IC) chip packaging, and more particularly, to a structure and method of forming a glass interposer having thermally conductive vias in addition to electrically conductive vias. The thermally conductive vias help dissipate heat from one or more IC chips, through the glass interposer, into an organic carrying, and then, into an underlying substrate where it can be dissipated.

Abstract: A structure and method for fabricating a laterally configured thin film varistor surge protection device using low temperature sputtering techniques which do not damage IC device components contiguous to the varistor being fabricated. The lateral thin film varistor may include a continuous layer of alternating regions of a first metal oxide layer and a second metal oxide layer formed between two laterally spaced electrodes using a low temperature sputtering process followed by a low temperature annealing process.

Abstract: A structure and method for fabricating a laterally configured thin film varistor surge protection device using low temperature sputtering techniques which do not damage IC device components contiguous to the varistor being fabricated. The lateral thin film varistor may consist of a continuous layer of alternating regions of a first metal oxide layer and a second metal oxide layer formed between two laterally spaced electrodes using a low temperature sputtering process followed by a low temperature annealing process.

Abstract: An optofluidic architecture for label free, highly parallel, detection of molecular interactions is based on the use of optically resonant devices whose resonant wavelength is shifted due to a local change in refractive index caused by a positive binding event between a surface bound molecule and its solution phase target. These devices have an extremely low limit of detection and are compatible with aqueous environments. The device combines the sensitivity (limit of detection) of nanosensor technology with the parallelity of the microarray type format.

Abstract: A chip fabricated from a semiconductor material is disclosed, which may include active devices located below a first depth from the chip back side, and a structure to remove heat from the active devices to the chip back side. The structure may include thermally conductive partial vias (TCPVs), which may include a recess with a depth, from the chip back side towards the active devices less than the first depth. Each TCPV may include a barrier layer deposited within the recess and deposited upon the back side of the chip. Each TCPV may also include a thermally conductive layer deposited upon the barrier layer. The structure may also include through-silicon vias (TSVs) electrically connected to active devices, extending from the back side to an active device side of the chip to conductively remove heat from the active devices to the back side of the chip.

Abstract: A structure and method for fabricating a laterally configured thin film varistor surge protection device using low temperature sputtering techniques which do not damage IC device components contiguous to the varistor being fabricated. The lateral thin film varistor may consist of a continuous layer of alternating regions of a first metal oxide layer and a second metal oxide layer formed between two laterally spaced electrodes using a low temperature sputtering process followed by a low temperature annealing process.

Abstract: As disclosed herein, a method, executed by a computer, for integrated circuit timing variability reduction includes loading a netlist that corresponds to a chip design, where the chip design includes one or more circuits and a plurality of post-fill features, traversing a portion of the netlist corresponding to a circuit, determining a post-fill environment for the circuit from a plurality of post-fill features, and modeling a timing variance for the circuit based on the post-fill environment. The method may also include changing one or more post-fill features to achieve a targeted delay. The method may include generating a report of circuit timing and timing variances. One or more circuits can be concurrently traversed. The timing variance can be modeled with the use of a scaling factor for a standard timing variance. A computer system and computer program product corresponding to the method are also disclosed herein.

Abstract: A chip fabricated from a semiconductor material is disclosed. The chip may include active devices located below a first depth from a chip back side and a structure configured to remove heat from the chip. The structure may include microvias electrically insulated from the active devices and having a second depth, less than the first depth, from the back side towards the active devices. Each microvia may also have a fill material having a thermal conductivity greater than a semiconductor thermal conductivity. The structure may also include thermally conductive material regions on the back side of the chip in contact with sets of microvias. The structure may also include through-silicon vias electrically connected to the active devices, and extending from the back side to an active device side of the chip and configured to remove heat from the active devices to the back side of the chip.

Abstract: Embodiments of the disclosure relate to X-ray imaging systems. In one embodiment, the X-ray imaging system features a target configured to receive a focused electron beam from an electron emitter and emit a line source X-ray beam as a result of receiving the focused electron beam; and a monochromator crystal configured to receive the line source X-ray beam from the target and diffract only a portion of the X-rays, wherein the portion of X-rays satisfies the Bragg diffraction condition for the monochromator crystal, and wherein the monochromator crystal is oriented relative to the target such that the portion of the X-rays from the target that satisfy the Bragg condition illuminate an entire length of a surface of the monochromator crystal.

Abstract: In one embodiment, an X-ray source is provided that includes one or more electron emitters configured to emit one or more electron beams and one or more source targets configured to receive the one or more electron beams emitted by the one or more electron emitters and, as a result of receiving the one or more electron beams, to emit X-rays. Each source target of the X-ray source includes a first layer having one or more first materials; and a second layer in thermal communication with the first layer and having one or more second materials. The first layer is positioned closer to the one or more emitters than the second layer, the first material has a higher overall thermal conductivity than the second layer, and the second layer produces the majority of the X-rays emitted by the source target.

Abstract: In one embodiment, an X-ray source is provided that includes one or more electron emitters configured to emit one or more electron beams and one or more source targets configured to receive the one or more electron beams emitted by the one or more electron emitters and, as a result of receiving the one or more electron beams, to emit X-rays. Each source target of the X-ray source includes a first layer having one or more first materials; and a second layer in thermal communication with the first layer and having one or more second materials. The first layer is positioned closer to the one or more emitters than the second layer, the first material has a higher overall thermal conductivity than the second layer, and the second layer produces the majority of the X-rays emitted by the source target.

Abstract: Embodiments of the disclosure relate to X-ray imaging systems. In one embodiment, the X-ray imaging system features a target configured to receive a focused electron beam from an electron emitter and emit a line source X-ray beam as a result of receiving the focused electron beam; and a monochromator crystal configured to receive the line source X-ray beam from the target and diffract only a portion of the X-rays, wherein the portion of X-rays satisfies the Bragg diffraction condition for the monochromator crystal, and wherein the monochromator crystal is oriented relative to the target such that the portion of the X-rays from the target that satisfy the Bragg condition illuminate an entire length of a surface of the monochromator crystal.

Abstract: An optical chromatography system employs fluid filled hollow core fibers, such as photonic crystal fibers (PCFs), which confine an incident optical beam from a laser, for example, in the core and cause separation of particles in the fluid along the length of the PCF. The incident optical beam is confined in the fluid filled core of the PCF by a periodic lattice of air capillaries surrounding the core. The lattice either creates a lower refractive index in the cladding than in the fluid filled core or creates a 1D photonic bandgap structure where the guiding is accomplished by surrounding the fluid filled core with a periodically changing array of dielectric constant which prohibits radial dilution of the optical energy over a range of wavelengths through photonic bandgap effects.

Abstract: An optofluidic architecture for label free, highly parallel, detection of molecular interactions is based on the use of optically resonant devices whose resonant wavelength is shifted due to a local change in refractive index caused by a positive binding event between a surface bound molecule and its solution phase target. These devices have an extremely low limit of detection and are compatible with aqueous environments. The device combines the sensitivity (limit of detection) of nanosensor technology with the parallelity of the microarray type format.