Abstract: Methods and server systems for computing fraud risk scores for various merchants associated with an acquirer described herein. The method performed by a server system includes accessing merchant-related transaction data including merchant-related transaction indicators associated with a merchant from a transaction database. Method includes generating a merchant-related transaction features based on the merchant-related indicators. Method includes generating via risk prediction models, for a payment transaction with the merchant, merchant health and compliance risk scores, merchant terminal risk scores, merchant chargeback risk scores, and merchant activity risk scores based on the merchant-related transaction features. Method includes facilitating transmission of a notification message to an acquirer server associated with the merchant.

Abstract: An example network manager receives, from a conductor switch of a switch stack, an active configuration. The network manager determines, based on the active configuration, switch model types for a plurality of switches of the switch stack. The network manager determines, based on the switch model types and the active configuration, a number of ports of the plurality of switches of the switch stack and a current configuration of each port of each switch of the switch stack. The network manager updates a device configuration element of a network management user interface to display the current configuration of each port of each switch of the switch stack in a manner that indicates that the switch stack is a single logical switch.

Abstract: A system and a method for automatically identifying key dialogues in media is disclosed herein. In the method disclosed herein, the key dialogues engine receives the media asset and extract transcript data and supplementary data. The key dialogues engine processes the transcript data into a plurality of transcript data elements and associate the transcript data elements with respective data elements selected from the supplementary data.

Abstract: An ionic redox transistor comprises a solid channel, a solid reservoir layer, and a solid electrolyte layer disposed between the channel and the reservoir layer. The channel exhibits a substantially linear current-voltage relationship in a first range of voltages, and a nonlinear current-voltage relationship in a second range of voltages that is greater than the first range of voltages. One or both of the substantially linear current-voltage relationship or the nonlinear current-voltage relationship of the channel is varied by changing the concentration of ions such as oxygen vacancies in the channel. Ion or vacancy transport between the channel and the reservoir layer across the electrolyte layer occurs in response to applying a voltage between the channel and the reservoir layer. Subject to the first range of voltages, the channel can function as a synapse device. Subject to the second range of voltages, the channel can function as a neuron device.

Abstract: An example network manager receives, from a conductor switch of a switch stack, an active configuration. The network manager determines, based on the active configuration, switch model types for a plurality of switches of the switch stack. The network manager determines, based on the switch model types and the active configuration, a number of ports of the plurality of switches of the switch stack and a current configuration of each port of each switch of the switch stack. The network manager updates a device configuration element of a network management user interface to display the current configuration of each port of each switch of the switch stack in a manner that indicates that the switch stack is a single logical switch.

Abstract: A method for performing learning is described. A free inference is performed on a learning network for input signals. The input signals correspond to target output signals. The learning network includes inputs that receive the input signals, neurons, weights interconnecting the neurons, and outputs. The learning network is described by an energy for the free inference. The energy includes an interaction term corresponding to interactions consisting of neuron pair interactions. The free inference results in output signals. A first portion of the plurality of weights corresponding to data flow for the free inference. A biased inference is performed on the learning network by providing the input signals to the inputs and bias signals to the outputs. The bias signals are based on the target output signals and the output signals. The bias signals are fedback to the learning network through a second portion of the weights corresponding to a transpose of the first portion of the weights.

Abstract: a Systems and methods are provided for matrix tiling to accelerate computing in redundant matrices. The method may include identifying unique submatrices in the matrix; loading values of elements of each unique submatrix into a respective one of the array processors; applying the vector to inputs of each of the array processors; and adding outputs of the array processors according to locations of the unique submatrices in the matrix.

Abstract: A method for determining a solution to a constrained optimization problem includes programming a weights matrix of a Hopfield network with a first encoded matrix representation of an initial constrained optimization problem. The method also includes employing the Hopfield network to determine a solution to the initial constrained optimization problem. Additionally, the method includes encoding a plurality of constrained optimization problems associated with a target constrained optimization problem into a plurality of encoded matrix representations each of which are a combination of the first and the second encoded matrix representations. The plurality of encoded matrix representations increases in convergence to the second encoded matrix representation of the target constrained optimization problem sequentially. The method further includes re-programming the weights matrix of the Hopfield network in an iterative manner with the plurality of encoded matrix representations.

Abstract: A memristive device is described. The memristive device includes a first layer having a first plurality of conductive lines, a second layer having a second plurality of conductive lines, and memristive interlayer connectors. The first and second layers differ. The first and second pluralities of conductive lines are each lithographically defined. The first and second pluralities of conductive lines are insulated from each other. The memristive interlayer connectors are memristively coupled with a first portion of the first plurality of conductive lines and memristively coupled with a second portion of the second plurality of conductive lines. The memristive interlayer connectors are thus sparsely coupled with the first and second pluralities of conductive lines. Each memristive interlayer connector includes a conductive portion and a memristive portion.

Abstract: A method for performing learning is described. A free inference is performed on a learning network for input signals. The input signals correspond to target output signals. The learning network includes inputs that receive the input signals, neurons, weights interconnecting the neurons, and outputs. The learning network is described by an energy for the free inference. The energy includes an interaction term corresponding to interactions consisting of neuron pair interactions. The free inference results in output signals. A first portion of the plurality of weights corresponding to data flow for the free inference. A biased inference is performed on the learning network by providing the input signals to the inputs and bias signals to the outputs. The bias signals are based on the target output signals and the output signals. The bias signals are fedback to the learning network through a second portion of the weights corresponding to a transpose of the first portion of the weights.

Abstract: Systems and methods are provided for implementing a hardware accelerator. The hardware accelerator emulates a neural network, and includes a memristor crossbar array, and a non-linear filter. The memristor crossbar array can be programmed to calculate node values of the neural network. The nodes values can be calculated in accordance with rules to reduce an energy function associated with the neural network. The non-linear filter is coupled to the memristor crossbar array and programmed to harness noise signals that may be present in analog circuitry of the hardware accelerator. The noise signals can be harnessed such that the energy function associated with the neural network converges towards a global minimum and modifies the calculated node values. In some embodiments, the non-liner filter is implemented as a Schmidt trigger comparator.

Abstract: A memristive device is described. The memristive device includes a first layer having a first plurality of conductive lines, a second layer having a second plurality of conductive lines, and memristive interlayer connectors. The first and second layers differ. The first and second pluralities of conductive lines are each lithographically defined. The first and second pluralities of conductive lines are insulated from each other. The memristive interlayer connectors are memristively coupled with a first portion of the first plurality of conductive lines and memristively coupled with a second portion of the second plurality of conductive lines. The memristive interlayer connectors are thus sparsely coupled with the first and second pluralities of conductive lines. Each memristive interlayer connector includes a conductive portion and a memristive portion.

Abstract: Recurrent neural networks, and methods therefor, are provided with diagonal and programming fluctuation to find energy global minima. The method may include storing the matrix of weights in memory cells of a crossbar array of a recursive neural network prior to operation of the recursive neural network; altering the weights according to a probability distribution; setting the weights to non-zero values in at least one of the memory cells in a diagonal of the memory cells in the crossbar array; and operating the recursive neural network.

Abstract: Systems are provided for implementing a hardware accelerator. The hardware accelerator emulate a stochastic neural network, and includes a first memristor crossbar array, and a second memristor crossbar array. The first memristor crossbar array can be programmed to calculate node values of the neural network. The nodes values can be calculated in accordance with rules to reduce an energy function associated with the neural network. The second memristor crossbar array is coupled to the first memristor crossbar array and programmed to introduce noise signals into the neural network. The noise signals can be introduced such that the energy function associated with the neural network converges towards a global minimum and modifies the calculated node values.

Abstract: A memristive device and mechanisms for providing and using the memristive device are described. The memristive device includes a nanowire, a plurality of memristive plugs and a plurality of electrodes. The nanowire has a conductive core and an insulator coating at least a portion of the conductive core. The insulator has a plurality of apertures therein. The memristive plugs are for the apertures. At least a portion of each of the memristive plugs resides in each of the apertures. The memristive plugs are between the conductive core and the electrodes.

Abstract: Systems and methods are configured to provide a first problem to be solved to a network of memristors. A second problem to be solved can be gradually provided to the network of memristors. Controlled noise can be applied to the network of memristors for at least a portion of time during which the second problem is “gradually” provided to the network of memristors. A solution to the second problem can be determined.

Abstract: Staged neural networks and methods are described herein. In some embodiments, the methods may identify a plurality of second NP hard/complete problems that are similar to the first NP hard/complete problem and identify solutions to the second NP hard/complete problems. The methods may train a deep neural network with the second NP hard/complete problems and the solutions. The methods may provide the first NP hard/complete problem to the trained deep neural network to generate a preliminary solution to the first NP hard/complete problem and provide the preliminary solution to a recursive neural network configured to execute an energy minimization search. The recursive neural network may generate a final solution to the problem based on the preliminary solution.

Abstract: A DPE memristor crossbar array system includes a plurality of partitioned memristor crossbar arrays. Each of the plurality of partitioned memristor crossbar arrays includes a primary memristor crossbar array and a redundant memristor crossbar array. The redundant memristor crossbar array includes values that are mathematically related to values within the primary memristor crossbar array. In addition, the plurality of partitioned memristor crossbar arrays includes a block of shared analog circuits coupled to the plurality of partitioned memristor crossbar arrays. The block of shared analog circuits is to determine a dot product value of voltage values generated by at least one partitioned memristor crossbar array of the plurality of partitioned memristor crossbar arrays.

Abstract: A memristive device and mechanisms for providing and using the memristive device are described. The memristive device includes a nanowire, a plurality of memristive plugs and a plurality of electrodes. The nanowire has a conductive core and an insulator coating at least a portion of the conductive core. The insulator has a plurality of apertures therein. The memristive plugs are for the apertures. At least a portion of each of the memristive plugs resides in each of the apertures. The memristive plugs are between the conductive core and the electrodes.

Abstract: Systems, methods and mechanisms for efficiently calibrating memory signals. In various embodiments, a computing system includes at least one processor, a memory and a power manager. The power manager generates and sends updated power-performance states (p-states) to the processor and the memory. Logic within a memory controller for the memory initializes a first timer corresponding to a first p-state of the multiple p-states to indicate a duration for skipping memory calibration. The logic continues to update the first timer while transferring data with the memory using operating parameters of the first p-state. When the memory is not using operating parameters of the first p-state, the logic prevents updates of the first timer. When the power manager determines to transition the memory from the first p-state to a second p-state, and the second timer for the second e-state has not expired, the logic prevents calibration of the memory.