Patents by Inventor Suhas Kumar
Suhas Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11450712Abstract: A memristive device and mechanisms for providing and using the memristive device are described. The memristive device includes a nanowire, a plurality of memristive plugs and a plurality of electrodes. The nanowire has a conductive core and an insulator coating at least a portion of the conductive core. The insulator has a plurality of apertures therein. The memristive plugs are for the apertures. At least a portion of each of the memristive plugs resides in each of the apertures. The memristive plugs are between the conductive core and the electrodes.Type: GrantFiled: February 18, 2020Date of Patent: September 20, 2022Assignee: Rain Neuromorphics Inc.Inventors: Jack David Kendall, Suhas Kumar, Nikita Gaur
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Patent number: 11226752Abstract: Systems, methods and mechanisms for efficiently calibrating memory signals. In various embodiments, a computing system includes at least one processor, a memory and a power manager. The power manager generates and sends updated power-performance states (p-states) to the processor and the memory. Logic within a memory controller for the memory initializes a first timer corresponding to a first p-state of the multiple p-states to indicate a duration for skipping memory calibration. The logic continues to update the first timer while transferring data with the memory using operating parameters of the first p-state. When the memory is not using operating parameters of the first p-state, the logic prevents updates of the first timer. When the power manager determines to transition the memory from the first p-state to a second p-state, and the second timer for the second e-state has not expired, the logic prevents calibration of the memory.Type: GrantFiled: March 5, 2019Date of Patent: January 18, 2022Assignee: Apple Inc.Inventors: Rakesh L. Notani, Robert E. Jeter, Suhas Kumar Suvarna Ramesh, Naveen Kumar Korada, Mohammad Rizwan, Alma L. Juarez Dominguez, John H. Kelm, Matthew R. Johnson
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Publication number: 20210406656Abstract: A memristive device is described. The memristive device includes a first layer having a first plurality of conductive lines, a second layer having a second plurality of conductive lines, and memristive interlayer connectors. The first and second layers differ. The first and second pluralities of conductive lines are each lithographically defined. The first and second pluralities of conductive lines are insulated from each other. The memristive interlayer connectors are memristively coupled with a first portion of the first plurality of conductive lines and memristively coupled with a second portion of the second plurality of conductive lines. The memristive interlayer connectors are thus sparsely coupled with the first and second pluralities of conductive lines. Each memristive interlayer connector includes a conductive portion and a memristive portion.Type: ApplicationFiled: June 22, 2021Publication date: December 30, 2021Inventors: Suhas Kumar, Jack David Kendall, Alexander Almela Conklin
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Publication number: 20210257411Abstract: A memristive device and mechanisms for providing and using the memristive device are described. The memristive device includes a nanowire, a plurality of memristive plugs and a plurality of electrodes. The nanowire has a conductive core and an insulator coating at least a portion of the conductive core. The insulator has a plurality of apertures therein. The memristive plugs are for the apertures. At least a portion of each of the memristive plugs resides in each of the apertures. The memristive plugs are between the conductive core and the electrodes.Type: ApplicationFiled: February 18, 2020Publication date: August 19, 2021Inventors: Jack David Kendall, Suhas Kumar, Nikita Gaur
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Publication number: 20210225440Abstract: A DPE memristor crossbar array system includes a plurality of partitioned memristor crossbar arrays. Each of the plurality of partitioned memristor crossbar arrays includes a primary memristor crossbar array and a redundant memristor crossbar array. The redundant memristor crossbar array includes values that are mathematically related to values within the primary memristor crossbar array. In addition, the plurality of partitioned memristor crossbar arrays includes a block of shared analog circuits coupled to the plurality of partitioned memristor crossbar arrays. The block of shared analog circuits is to determine a dot product value of voltage values generated by at least one partitioned memristor crossbar array of the plurality of partitioned memristor crossbar arrays.Type: ApplicationFiled: April 6, 2021Publication date: July 22, 2021Inventors: Amit S. Sharma, John Paul Strachan, Catherine Graves, Suhas Kumar, Craig Warner, Martin Foltin
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Patent number: 11024379Abstract: Systems and methods for providing write process optimization for memristors are described. Write process optimization circuitry manipulates the memristor's write operation, allowing the number of cycles in the write process is reduced. Write process optimization circuitry can include write current integration circuitry that measures an integral of a write current over time. The write optimization circuitry can also include shaping circuitry. The shaping circuitry can shape a write pulse, by determining the pulse's termination, width, and slope. The write pulse is shaped depending upon whether the target memristor device exhibits characteristics of “maladroit” cells or “adroit” cells. The pulse shaping circuitry uses the integral and measured write current to terminate the write pulse in a manner that allows the memristor, wherein having maladroit cells and adroit cells, to reach a target state.Type: GrantFiled: October 29, 2019Date of Patent: June 1, 2021Assignee: Hewlett Packard Enterprise Development LPInventors: Amit Sharma, John Paul Strachan, Suhas Kumar, Catherine Graves, Martin Foltin, Craig Warner
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Publication number: 20210125667Abstract: Systems and methods for providing write process optimization for memristors are described. Write process optimization circuitry manipulates the memristor's write operation, allowing the number of cycles in the write process is reduced. Write process optimization circuitry can include write current integration circuitry that measures an integral of a write current over time. The write optimization circuitry can also include shaping circuitry. The shaping circuitry can shape a write pulse, by determining the pulse's termination, width, and slope. The write pulse is shaped depending upon whether the target memristor device exhibits characteristics of “maladroit” cells or “adroit” cells. The pulse shaping circuitry uses the integral and measured write current to terminate the write pulse in a manner that allows the memristor, wherein having maladroit cells and adroit cells, to reach a target state.Type: ApplicationFiled: October 29, 2019Publication date: April 29, 2021Inventors: AMIT SHARMA, JOHN PAUL STRACHAN, SUHAS KUMAR, CATHERINE GRAVES, MARTIN FOLTIN, CRAIG WARNER
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Patent number: 10984860Abstract: A DPE memristor crossbar array system includes a plurality of partitioned memristor crossbar arrays. Each of the plurality of partitioned memristor crossbar arrays includes a primary memristor crossbar array and a redundant memristor crossbar array. The redundant memristor crossbar array includes values that are mathematically related to values within the primary memristor crossbar array. In addition, the plurality of partitioned memristor crossbar arrays includes a block of shared analog circuits coupled to the plurality of partitioned memristor crossbar arrays. The block of shared analog circuits is to determine a dot product value of voltage values generated by at least one partitioned memristor crossbar array of the plurality of partitioned memristor crossbar arrays.Type: GrantFiled: March 26, 2019Date of Patent: April 20, 2021Assignee: Hewlett Packard Enterprise Development LPInventors: Amit S. Sharma, John Paul Strachan, Catherine Graves, Suhas Kumar, Craig Warner, Martin Foltin
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Publication number: 20210103802Abstract: Examples disclosed herein relate to a memristor matrix comprising a crossbar array, a multiplexer and a noise control circuit. The noise control circuit may comprise a threshold comparator and a threshold feedback circuit to receive a first threshold and a second threshold and output a threshold signal based, in part, on an output of the threshold comparator.Type: ApplicationFiled: October 4, 2019Publication date: April 8, 2021Inventors: Suhas Kumar, John Paul Strachan
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Patent number: 10949738Abstract: A memristor matrix comprising a crossbar array, a multiplexer and a noise control circuit. The noise control circuit may comprise a threshold comparator and a threshold feedback circuit to receive a first threshold and a second threshold and output a threshold signal based, in part, on an output of the threshold comparator.Type: GrantFiled: October 4, 2019Date of Patent: March 16, 2021Assignee: Hewlett Packard Enterprise Development LPInventors: Suhas Kumar, John Paul Strachan
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Patent number: 10930343Abstract: A memristor device includes a first electrode, a second electrode, and a memristor layer disposed between the first electrode and the second electrode. The memristor layer is formed of a metal oxide. The memristor layer includes a plurality of regions that extend between the first electrode and the second electrode. The plurality of regions of the memristor layer are created with different concentrations of oxygen before electrical operation, and, during electrical operation, a voltage-conductance characteristic of the memristor device is controlled based on the different concentrations of oxygen of the plurality of regions. The controlling of the voltage-conductance characteristic includes increasing or decreasing the conductance of the memristor device toward a target conductance at a specific voltage.Type: GrantFiled: August 21, 2018Date of Patent: February 23, 2021Assignee: Hewlett Packard Enterprise Development LPInventors: Amit S. Sharma, Suhas Kumar, Xia Sheng
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Patent number: 10885430Abstract: A non-Boolean analog system includes a first Mott memristor having a first value of a characteristic, and a second Mott memristor having a second value of the characteristic different than the first value. The system includes a resistance in series with the first and second Mott memristors to form a network having a capacitance and that is operable as a relaxation oscillator. Responsive to electrical excitation, a temperature of the network operating an environment including ambient thermal noise settles at an equilibrium corresponding to a global minimum that is a maximally optimal global solution to a global optimization problem to which the network corresponds.Type: GrantFiled: July 31, 2017Date of Patent: January 5, 2021Assignee: Hewlett Packard Enterprise Development LPInventor: Suhas Kumar
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Publication number: 20200364178Abstract: a Systems and methods are provided for matrix tiling to accelerate computing in redundant matrices. The method may include identifying unique submatrices in the matrix; loading values of elements of each unique submatrix into a respective one of the array processors; applying the vector to inputs of each of the array processors; and adding outputs of the array processors according to locations of the unique submatrices in the matrix.Type: ApplicationFiled: July 31, 2020Publication date: November 19, 2020Inventors: Suhas Kumar, Rui Liu
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Publication number: 20200334523Abstract: Systems and methods are provided for implementing a hardware accelerator. The hardware accelerator emulates a neural network, and includes a memristor crossbar array, and a non-linear filter. The memristor crossbar array can be programmed to calculate node values of the neural network. The nodes values can be calculated in accordance with rules to reduce an energy function associated with the neural network. The non-linear filter is coupled to the memristor crossbar array and programmed to harness noise signals that may be present in analog circuitry of the hardware accelerator. The noise signals can be harnessed such that the energy function associated with the neural network converges towards a global minimum and modifies the calculated node values. In some embodiments, the non-liner filter is implemented as a Schmidt trigger comparator.Type: ApplicationFiled: April 17, 2019Publication date: October 22, 2020Inventors: Suhas Kumar, Thomas Van Vaerenbergh, John Paul Strachan
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Publication number: 20200312406Abstract: A DPE memristor crossbar array system includes a plurality of partitioned memristor crossbar arrays. Each of the plurality of partitioned memristor crossbar arrays includes a primary memristor crossbar array and a redundant memristor crossbar array. The redundant memristor crossbar array includes values that are mathematically related to values within the primary memristor crossbar array. In addition, the plurality of partitioned memristor crossbar arrays includes a block of shared analog circuits coupled to the plurality of partitioned memristor crossbar arrays. The block of shared analog circuits is to determine a dot product value of voltage values generated by at least one partitioned memristor crossbar array of the plurality of partitioned memristor crossbar arrays.Type: ApplicationFiled: March 26, 2019Publication date: October 1, 2020Inventors: Amit S. Sharma, John Paul Strachan, Catherine Graves, Suhas Kumar, Craig Warner, Martin Foltin
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Publication number: 20200285406Abstract: Systems, methods and mechanisms for efficiently calibrating memory signals. In various embodiments, a computing system includes at least one processor, a memory and a power manager. The power manager generates and sends updated power-performance states (p-states) to the processor and the memory. Logic within a memory controller for the memory initializes a first timer corresponding to a first p-state of the multiple p-states to indicate a duration for skipping memory calibration. The logic continues to update the first timer while transferring data with the memory using operating parameters of the first p-state. When the memory is not using operating parameters of the first p-state, the logic prevents updates of the first timer. When the power manager determines to transition the memory from the first p-state to a second p-state, and the second timer for the second e-state has not expired, the logic prevents calibration of the memory.Type: ApplicationFiled: March 5, 2019Publication date: September 10, 2020Inventors: Rakesh L. Notani, Robert E. Jeter, Suhas Kumar Suvarna Ramesh, Naveen Kumar Korada, Mohammad Rizwan, Alma L. Juarez Dominguez, John H. Kelm, Matthew R. Johnson
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Patent number: 10762035Abstract: Systems and methods are provided for matrix tiling to accelerate computing in redundant matrices. The method may include identifying unique submatrices in the matrix; loading values of elements of each unique submatrix into a respective one of the array processors; applying the vector to inputs of each of the array processors; and adding outputs of the array processors according to locations of the unique submatrices in the matrix.Type: GrantFiled: February 8, 2019Date of Patent: September 1, 2020Assignee: Hewlett Packard Enterprise Development LPInventors: Suhas Kumar, Rui Liu
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Publication number: 20200257653Abstract: Systems and methods are provided for matrix tiling to accelerate computing in redundant matrices. The method may include identifying unique submatrices in the matrix; loading values of elements of each unique submatrix into a respective one of the array processors; applying the vector to inputs of each of the array processors; and adding outputs of the array processors according to locations of the unique submatrices in the matrix.Type: ApplicationFiled: February 8, 2019Publication date: August 13, 2020Inventors: SUHAS KUMAR, RUI LIU
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Publication number: 20200242448Abstract: Staged neural networks and methods therefor are provided for solving NP hard/complete problems. In some embodiments, the methods include identifying a plurality of second NP hard/complete problems, wherein each of the second NP hard/complete problems is similar to the first NP hard/complete problem; identifying solutions to the second NP hard/complete problems; training a deep neural network with the second NP hard/complete problems and the solutions; providing the first NP hard/complete problem to the trained deep neural network, wherein the trained deep neural network generates a preliminary solution to the first NP hard/complete problem; and providing the preliminary solution to a recursive neural network configured to execute an energy minimization search, wherein the recursive neural network generates a final solution to the problem based on the preliminary solution.Type: ApplicationFiled: January 29, 2019Publication date: July 30, 2020Inventors: JOHN PAUL STRACHAN, SUHAS KUMAR, THOMAS VAN VAERENBERGH
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Publication number: 20200242447Abstract: Recurrent neural networks, and methods therefor, are provided with diagonal and programming fluctuation to find energy global minima. The method may include storing the matrix of weights in memory cells of a crossbar array of a recursive neural network prior to operation of the recursive neural network; altering the weights according to a probability distribution; setting the weights to non-zero values in at least one of the memory cells in a diagonal of the memory cells in the crossbar array; and operating the recursive neural network.Type: ApplicationFiled: January 29, 2019Publication date: July 30, 2020Inventors: Suhas Kumar, Thomas Van Vaerenbergh, John Paul Strachan