Abstract: Apparatuses, systems, and methods for reset of row hammer detector circuits. A row hammer detector circuit includes a hash circuit configured to store a hash key and provide a first count value based on a hash between the hash key and a row address corresponding to a row of memory cells of a memory array. The row hammer detector circuit is configured to provide a match signal in response to the count value exceeding a threshold to cause a targeted refresh of a victim row adjacent the row of memory cells. In response to exit from a self-refresh mode, the hash circuit is configured to update the stored hash key with a new hash key.

Abstract: A memory performs a sequence of ECS operations to read a codeword, detect and correct any errors, and write the corrected codeword back to the memory array. An ECS circuit counts errors which are detected, and sets a value of one or more ECS registers in a mode register if the count exceeds a threshold filter at the end of the ECS cycle. The memory also includes a forced ECS readout circuit, which responsive to a command, for example from a controller, sets the value(s) in the ECS register(s).

Abstract: Apparatuses, systems, and methods for dynamically allocated aggressor detection. A memory may include an aggressor address storage structure which tracks access patterns to row addresses and their associated bank addresses. These may be used to determine if a row and bank address received as part of an access operation are an aggressor row and bank address. The aggressor row address may be used to generate a refresh address for a bank identified by the aggressor bank address. Since the aggressor storage structure tracks both row and bank addresses, its storage space may be dynamically allocated between banks based on access patterns to those banks.

Abstract: Apparatuses, systems, and methods for memory module data drives. A memory module includes a number of memory devices as well as module logic. Each memory device provides data by driving voltages along a data bus with a data bus driver of the memory device. An output driver, which is located on the module logic receives the voltages along the data bus and drives voltages of an external data terminal to output the data. The output driver may have a greater drive strength than the data bus driver.

Abstract: Apparatuses, systems, and methods for multi-bit error detection. A memory device may store data bits and parity bits in a memory array. An error correction code (ECC) circuit may generate syndrome bits based on the data and parity bits and use the syndrome bits to correct up to a single bit error in the data and parity bits. A multi-bit error (MBE) detection circuit may detect an MBE in the data and parity based on at least one of the syndrome bits or the parity bits. For example, the MBE detection circuit may determine if the syndrome bits have a mapped or unmapped state and/or may compare the parity bits, data bits, and an additional parity bit to determine if there is an MBE. When an MBE is detected an MBE signal is activated. In some embodiments, an MBE flag may be set based on the MBE signal being active.

Abstract: Memory devices and systems with memory-initiated command insertion (and associated methods) are disclosed herein. In one embodiment, a memory device comprises a command insertion terminal configured to be operably connected to a memory controller. The memory device can (i) identify a condition that can be addressed by receiving a command from the memory controller, and (ii) output, via the command insertion terminal, the command or an indication of the condition such that the command is inserted into a command queue of the memory controller. The memory device can include a command terminal over which the memory device can receive the command from the memory controller after the command is inserted in the command queue. In some embodiments, the condition can be a memory region of the memory device requiring a refresh cycle, and the command can be a command to perform a refresh cycle on the memory region.

Abstract: Memory systems with a communications bus (and associated systems, devices, and methods) are disclosed herein. In one embodiment, a memory device includes an input/output terminal separate from data terminals of the memory device. The input/output terminal can be operably connected to a memory controller via a communications bus. The memory device can be configured to initiate a communication with the memory controller by outputting a signal via the input/output terminal and/or over the communications bus. The memory device can be configured to output the signal in accordance with a clock signal that is different from a second clock signal user to output or receive data signals via the data terminals. In some embodiments, the memory device is configured to initiate communications over the communication bus only when it possesses a communication token. The communication token can be transferred between memory devices operably connected to the communications bus.

Abstract: Apparatuses, systems, and methods for dynamically allocated aggressor detection. A memory may include an aggressor address storage structure which tracks access patterns to row addresses and their associated bank addresses. These may be used to determine if a row and bank address received as part of an access operation are an aggressor row and bank address. The aggressor row address may be used to generate a refresh address for a bank identified by the aggressor bank address. Since the aggressor storage structure tracks both row and bank addresses, its storage space may be dynamically allocated between banks based on access patterns to those banks.

Abstract: Apparatuses, systems, and methods for sketch circuits for refresh binning. The rows of a memory may have different information retention times. The row addresses may be sorted into different bins based on these information retention times. In order to store information about which row addresses are associated with which bins a sketch circuit may be used. When an address is generated as part of a refresh operation, it may be used to generate a number of different hash values, which may be used to index entries in a storage structure. The entries may indicate which bin the address is associated with. Based on the binning information, the memory may refresh the address at different rates (e.g., by determining whether to provide the address as a refresh address or not).

Abstract: Apparatuses, systems, and methods for dynamically allocated aggressor detection. A memory may include an aggressor address storage structure which tracks access patterns to row addresses and their associated bank addresses. These may be used to determine if a row and bank address received as part of an access operation are an aggressor row and bank address. The aggressor row address may be used to generate a refresh address for a bank identified by the aggressor bank address. Since the aggressor storage structure tracks both row and bank addresses, its storage space may be dynamically allocated between banks based on access patterns to those banks.

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described in which waterfall attacks can be prevented from degrading data by alerting a memory controller that the memory device requests time to perform internal management operations, and should not be sent any further commands (e.g., activate commands) for a predetermined amount of time. In one embodiment, a memory device includes an external pin, a mode register, a memory array including a plurality of rows of memory cells, and circuitry configured to: determine that a criterion to perform an internal management operation on a subset of the plurality of rows has been met, transmit, in response to determining the criterion has been met, a signal to the external pin, determine a duration corresponding to the internal management operation, and write a bit value indicative of the determined duration to the mode register.

Abstract: Systems, methods and apparatus are provided for decoupling capacitors for an array of vertically stacked memory cells. Embodiments provide that the decoupling capacitors are electrically coupled to a power bus.

Abstract: Apparatuses and methods for tracking all row accesses in a memory device over time may be used to identify rows which are being hammered so that ‘victim’ rows may be identified and refreshed. A register stack may include a number of count values, each of which may track a number of accesses to a portion of the word lines of the memory device. Anytime a row within a given portion is accessed, the associated count value may be incremented. When a count value exceeds a first threshold, a second stack with a second number of count values may be used to track numbers of accesses to sub-portions of the given portion. When a second count value exceeds a second threshold, victim addresses may be provided to refresh the victim word lines associated with any of the word lines within the sub-portion.

Abstract: Apparatuses, systems, and methods for probabilistic data structures for error tracking. A memory device may include an error code correction (ECC) circuit which determines if data read from a memory array includes an error. If it does, the row address associated with the read data is provided to an error tracking circuit. The error tracking circuit may use probabilistic data structures, such as multiple count values, each indexed by different hash values of the row address. The count values may be used to determine if a given row address is repeatedly associated with errors. The memory may store these identified problem addresses in a data storage structure for example for diagnostic and/or repair purposes.

Abstract: Apparatuses, systems, and methods for a memory-directed access pause. A controller may perform access operations on a memory by providing commands and addresses. The memory may monitor the addresses to determine if one or more forms of attack (deliberate or inadvertent) is occurring. If an attack is detected, the memory may issue an alert signal (e.g., along an alert bus) and also provide pause data (e.g., along a data bus). The pause data may specify a length of time, and responsive to the alert and the pause data, the controller may suspend access operations on the memory for the length of time specified in the pause data. The memory may use the time when access operations are paused to refresh itself, for example to heal the damage caused by the attack).

Abstract: Embodiments disclosed herein relate to level shifters of a memory device. Specifically, the level shifters include a first series arrangement of transistors to offset a first transistor. The level shifters also include a second series arrangement of transistors to offset a second transistor. The first series arrangement is opposite the second series arrangement. The output of the first series arrangement is coupled to a first pull-up transistor and configured to cut off a pull-up of the first pull-up transistor to a first voltage. The output of the second series arrangement is coupled to a second pull-up transistor and configured to cut off a pull-up of the second pull-up transistor to the first voltage. The first series arrangement and the second series arrangement are coupled to a second voltage at different times. The series arrangements of transistors enable faster level shifting over conventional level shifters.

Abstract: Apparatuses, systems, and methods for updating hash values in a memory. A memory device may include one or more hash circuits, each of which may generate a hash value based on an input, such as a row address, and a set of hash keys. To increase the unpredictability of operations in the memory, the hash keys may be changed responsive to one or more triggers. Example triggers may include, a power up/reset operation, a command issued to the memory, or internal logic of the memory (e.g., a timer). Responsive to one or more of these triggers, the hash keys may be regenerated. For example a new seed value may be generated and used by a random number generator to generate the new set of hash keys.

Abstract: Apparatuses, systems, and methods for probabilistic data structures for error tracking. A memory device may include an error code correction (ECC) circuit which determines if data read from a memory array includes an error. If it does, the row address associated with the read data is provided to an error tracking circuit. The error tracking circuit may use probabilistic data structures, such as multiple count values, each indexed by different hash values of the row address. The count values may be used to determine if a given row address is repeatedly associated with errors. The memory may store these identified problem addresses in a data storage structure for example for diagnostic and/or repair purposes.

Abstract: Apparatuses, systems, and methods for updating hash values in a memory. A memory device may include one or more hash circuits, each of which may generate a hash value based on an input, such as a row address, and a set of hash keys. To increase the unpredictability of operations in the memory, the hash keys may be changed responsive to one or more triggers. Example triggers may include, a power up/reset operation, a command issued to the memory, or internal logic of the memory (e.g., a timer). Responsive to one or more of these triggers, the hash keys may be regenerated. For example a new seed value may be generated and used by a random number generator to generate the new set of hash keys.

Abstract: Apparatuses, systems, and methods for reset of row hammer detector circuits. A row hammer detector circuit includes a hash circuit configured to store a hash key and provide a first count value based on a hash between the hash key and a row address corresponding to a row of memory cells of a memory array. The row hammer detector circuit is configured to provide a match signal in response to the count value exceeding a threshold to cause a targeted refresh of a victim row adjacent the row of memory cells. In response to exit from a self-refresh mode, the hash circuit is configured to update the stored hash key with a new hash key.