Abstract: Apparatus and methods for hybrid post package repair are disclosed. One such apparatus may include a package including memory cells and volatile memory. The volatile memory may be configured to store defective address data corresponding to a first portion of the memory cells that are deemed defective post-packaging. The apparatus may also include a decoder configured to select a second portion of the memory cells instead of the first portion of the memory cells when received current address data corresponding to an address to be accessed matches the defective address data stored in the volatile memory. The apparatus may also include non-volatile memory in the package. The apparatus may also include a mapping logic circuit in the package. The mapping logic circuit may be configured to program the replacement address data to the non-volatile memory subsequent to the defective address data being stored to the volatile memory.

Abstract: Apparatuses and methods for implementing masked write commands are disclosed herein. An example apparatus may include a memory bank, a local buffer circuit, and an address control circuit. The local buffer circuit may be associated with the memory bank. The address control circuit may be coupled to the memory bank and configured to receive a command and an address associated with the command. The address control circuit may include a global buffer circuit configured to store the address. The address control circuit may further be configured to delay the command using one of a plurality of command paths based, at least in part, on a write latency and to provide the address stored in the global buffer circuit to the local buffer circuit to be stored therein.

Abstract: Apparatus and methods for hybrid post package repair are disclosed. One such apparatus may include a package including memory cells and volatile memory. The volatile memory may be configured to store defective address data corresponding to a first portion of the memory cells that are deemed defective post-packaging. The apparatus may also include a decoder configured to select a second portion of the memory cells instead of the first portion of the memory cells when received current address data corresponding to an address to be accessed matches the defective address data stored in the volatile memory. The apparatus may also include non-volatile memory in the package. The apparatus may also include a mapping logic circuit in the package. The mapping logic circuit may be configured to program the replacement address data to the non-volatile memory subsequent to the defective address data being stored to the volatile memory.

Abstract: Apparatuses and methods for performing a data bus inversion operation (DBI) are described. An example apparatus includes a DBI circuit configured to, in parallel, determine preliminary DBI bits based on a block of data. Individual preliminary DBI bits are associated with respective sub-blocks of the block of data. The DBI circuit is further configured to serially determine DBI bits based on the preliminary DBI bits. Individual ones of the DBI bits are associated with respective ones of the sub-blocks. The DBI circuit is further configured to invert bits of individual sub-blocks responsive to the respective associated DBI bits having a particular logical value to provide DBI data. The apparatus further includes data outputs configured to serially output sub-blocks of the DBI data and the DBI bits.

Abstract: Apparatus and methods for hybrid post package repair are disclosed. One such apparatus may include a package including memory cells and volatile memory. The volatile memory may be configured to store defective address data corresponding to a first portion of the memory cells that are deemed defective post-packaging. The apparatus may also include a decoder configured to select a second portion of the memory cells instead of the first portion of the memory cells when received current address data corresponding to an address to be accessed matches the defective address data stored in the volatile memory. The apparatus may also include non-volatile memory in the package. The apparatus may also include a mapping logic circuit in the package. The mapping logic circuit may be configured to program the replacement address data to the non-volatile memory subsequent to the defective address data being stored to the volatile memory.

Abstract: Driver systems and methods are provided, such as those that include identifying a process corner of a driver; and configuring the driver based on the identified process corner. Further embodiments provide a method that includes detecting a process corner of a driver, setting a reference voltage of a calibration circuit based on the process corner detected, and configuring the driver based on the reference voltage.

Abstract: Apparatuses and methods for performing a data bus inversion operation (DBI) are described. An example apparatus includes a DBI circuit configured to, in parallel, determine preliminary DBI bits based on a block of data. Individual preliminary DBI bits are associated with respective sub-blocks of the block of data. The DBI circuit is further configured to serially determine DBI bits based on the preliminary DBI bits. Individual ones of the DBI bits are associated with respective ones of the sub-blocks. The DBI circuit is further configured to invert bits of individual sub-blocks responsive to the respective associated DBI bits having a particular logical value to provide DBI data. The apparatus further includes data outputs configured to serially output sub-blocks of the DBI data and the DBI bits.

Abstract: Apparatuses and methods for implementing masked write commands are disclosed herein. An example apparatus may include a memory bank, a local buffer circuit, and an address control circuit. The local buffer circuit may be associated with the memory bank. The address control circuit may be coupled to the memory bank and configured to receive a command and an address associated with the command. The address control circuit may include a global buffer circuit configured to store the address. The address control circuit may further be configured to delay the command using one of a plurality of command paths based, at least in part, on a write latency and to provide the address stored in the global buffer circuit to the local buffer circuit to be stored therein.

Abstract: There is provided a system and method for automatically calibrating a temperature sensor. More specifically, there is provided a system including a temperature sensor that includes a first resistance configured to indicate a temperature of the temperature sensor and a second resistance, in series with the first resistor, wherein the second resistance is adjustable to calibrate the first resistance, and a calibration circuit, coupled to the temperature sensor and configured to automatically calibrate the first resistance.

Abstract: There is provided a system and method for automatically calibrating a temperature sensor. More specifically, there is provided a system including a temperature sensor that includes a first resistance configured to indicate a temperature of the temperature sensor and a second resistance, in series with the first resistor, wherein the second resistance is adjustable to calibrate the first resistance, and a calibration circuit, coupled to the temperature sensor and configured to automatically calibrate the first resistance.

Abstract: Driver systems and methods are provided, such as those that include identifying a process corner of a driver; and configuring the driver based on the identified process corner. Further embodiments provide a method that includes detecting a process corner of a driver, setting a reference voltage of a calibration circuit based on the process corner detected, and configuring the driver based on the reference voltage.

Abstract: Driver systems and methods are provided, such as those that include identifying a process corner of a driver; and configuring the driver based on the identified process corner. Further embodiments provide a method that includes detecting a process corner of a driver, setting a reference voltage of a calibration circuit based on the process corner detected, and configuring the driver based on the reference voltage.

Abstract: A memory structure includes a plurality of address banks where each address bank is operative to store a memory address. In certain embodiments, at least two of the address banks share physical memory locations for at least one redundant most significant bit. Additionally, at least two of the address banks in certain embodiments share physical memory locations for at least one redundant most significant bit and at least one redundant least significant bit. At least two of the address banks in certain embodiments also share physical memory locations for at least one redundant interior bit.

Abstract: A memory structure includes a plurality of address banks where each address bank is operative to store a memory address. In certain embodiments, at least two of the address banks share physical memory locations for at least one redundant most significant bit. Additionally, at least two of the address banks in certain embodiments share physical memory locations for at least one redundant most significant bit and at least one redundant least significant bit. At least two of the address banks in certain embodiments also share physical memory locations for at least one redundant interior bit.

Abstract: There is provided a system and method for automatically calibrating a temperature sensor. More specifically, there is provided a system including a temperature sensor that includes a first resistance configured to indicate a temperature of the temperature sensor and a second resistance, in series with the first resistor, wherein the second resistance is adjustable to calibrate the first resistance, and a calibration circuit, coupled to the temperature sensor and configured to automatically calibrate the first resistance.

Abstract: A memory structure includes a plurality of address banks where each address bank is operative to store a memory address. In certain embodiments, at least two of the address banks share physical memory locations for at least one redundant most significant bit. Additionally, at least two of the address banks in certain embodiments share physical memory locations for at least one redundant most significant bit and at least one redundant least significant bit. At least two of the address banks in certain embodiments also share physical memory locations for at least one redundant interior bit.

Abstract: There is provided a system and method for automatically calibrating a temperature sensor. More specifically, there is provided a system made up of a temperature sensor which includes a first resistance configured to indicate a temperature of the temperature sensor and a second resistance, in series with the first resistor, wherein the second resistance is adjustable to calibrate the first resistance, and a calibration circuit, coupled to the temperature sensor and configured to automatically calibrate the first resistance.

Abstract: Apparatus including a reference circuit configured to provide a particular impedance and having a first plurality of switching devices and a resistive device coupled to each other in parallel; a second plurality of switching devices coupled to each other in parallel and coupled in series with the reference circuit between a supply node and a supply return node; and processing logic coupled to the second plurality of switching devices and configured to selectively enable and disable a combination of switching devices of the second plurality of switching devices that results in an impedance of the enabled switching devices more closely matching the particular impedance of the reference circuit than at least one other combination of enabled and disabled switching devices of the second plurality of switching devices.

Abstract: Apparatus including a reference circuit configured to provide a particular impedance and having a first plurality of switching devices and a resistive device coupled to each other in parallel; a second plurality of switching devices coupled to each other in parallel and coupled in series with the reference circuit between a supply node and a supply return node; and processing logic coupled to the second plurality of switching devices and configured to selectively enable and disable a combination of switching devices of the second plurality of switching devices that results in an impedance of the enabled switching devices more closely matching the particular impedance of the reference circuit than at least one other combination of enabled and disabled switching devices of the second plurality of switching devices.

Abstract: Driver systems and methods are provided, such as those that include identifying a process corner of a driver; and configuring the driver based on the identified process corner. Further embodiments provide a method that includes detecting a process corner of a driver, setting a reference voltage of a calibration circuit based on the process corner detected, and configuring the driver based on the reference voltage.