Patents by Inventor Sun-Jay Chang
Sun-Jay Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140183641Abstract: Disclosed are a FinFET diode of high efficiency, designed to resolve the degradation problem with a conventional FinFET diode arising from reduced active area, and a method of fabrication. The FinFET diode has a doped substrate, two spaced-apart groups of substantially parallel, equally-spaced, elongated semiconductor fin structures, dielectric layers formed between the two groups and among the fin structures for insulation, a plurality of substantially equal-spaced and parallel elongated gate structures perpendicularly traversing both groups of the fin structures, and two groups of semiconductor strips respectively formed lengthwise upon the two groups of the fin structures. The two groups of semiconductor strips are doped to have opposite conductivity types, p-type and n-type. The FinFET diode further has metal contacts formed upon the semiconductor strips. In an embodiment, the semiconductor strips may be integrally formed with the fin structures by epitaxial growth and in-situ doped.Type: ApplicationFiled: July 25, 2013Publication date: July 3, 2014Applicant: Taiwan Semiconductor Manufacturing Comapny, Ltd.Inventors: Hsueh-Shih Fan, Sun-Jay Chang, Chia-Hsin Hu, Min-Chang Liang, Shien-Yang Wu, Wen-Hsing Hsieh, Ching-Fang Huang
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Patent number: 8736355Abstract: A band gap reference circuit includes an error-amplifier-based current mirror coupled between a first supply node and a pair of intermediate voltage nodes, and a matched diode pair for providing a proportional-to-absolute temperature (PTAT) current. The matched diode pair includes a first diode connected between a first intermediate voltage node from the pair of intermediate voltage nodes and a second supply node, and a second diode connected in series with a resistor between a second intermediate voltage node from the pair of intermediate voltage nodes and the second supply node. Each diode has a P-N diode junction that is a homojunction.Type: GrantFiled: June 12, 2012Date of Patent: May 27, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jaw-Juinn Horng, Chung-Hui Chen, Sun-Jay Chang, Chia-Hsin Hu
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Publication number: 20140077230Abstract: A band gap reference circuit includes an error-amplifier-based current mirror coupled between a first supply node and a pair of intermediate voltage nodes, and a matched diode pair for providing a proportional-to-absolute temperature (PTAT) current. The matched diode pair includes a first diode connected between a first intermediate voltage node from the pair of intermediate voltage nodes and a second supply node, and a second diode connected in series with a resistor between a second intermediate voltage node from the pair of intermediate voltage nodes and the second supply node. Each diode has a P-N diode junction that is a homojunction.Type: ApplicationFiled: November 26, 2013Publication date: March 20, 2014Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jaw-Juinn HORNG, Chung-Hui CHEN, Sun-Jay CHANG, Chia-Hsin HU
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Publication number: 20140077331Abstract: A method of forming one or more diodes in a fin field-effect transistor (FinFET) device includes forming a hardmask layer having a fin pattern, said fin pattern including an isolated fin area, a fin array area, and a FinFET area. The method further includes etching a plurality of fins into a semiconductor substrate using the fin pattern, and depositing a dielectric material over the semiconductor substrate to fill spaces between the plurality of fins. The method further includes planarizing the semiconductor substrate to expose the hardmask layer. The method further includes implanting a p-type dopant into the fin array area and portions of the FinFET area, and implanting an n-type dopant into the isolated fin area, a portion of the of fin array area surrounding the p-well and portions of the FinFET area. The method further includes annealing the semiconductor substrate.Type: ApplicationFiled: November 25, 2013Publication date: March 20, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Hsin HU, Sun-Jay CHANG, Jaw-Juinn HORNG, Chung-Hui CHEN
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Patent number: 8610241Abstract: Diodes and bipolar junction transistors (BJTs) are formed in IC devices that include fin field-effect transistors (FinFETs) by utilizing various process steps in the FinFET formation process. The diode or BJT includes an isolated fin area and fin array area having n-wells having different depths and a p-well in a portion of the fin array area that surrounds the n-well in the isolated fin area. The n-wells and p-well for the diodes and BJTs are implanted together with the FinFET n-wells and p-wells.Type: GrantFiled: June 12, 2012Date of Patent: December 17, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Hsin Hu, Sun-Jay Chang, Jaw-Juinn Horng, Chung-Hui Chen
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Publication number: 20130328162Abstract: Diodes and bipolar junction transistors (BJTs) are formed in IC devices that include fin field-effect transistors (FinFETs) by utilizing various process steps in the FinFET formation process. The diode or BJT includes an isolated fin area and fin array area having n-wells having different depths and a p-well in a portion of the fin array area that surrounds the n-well in the isolated fin area. The n-wells and p-well for the diodes and BJTs are implanted together with the FinFET n-wells and p-wells.Type: ApplicationFiled: June 12, 2012Publication date: December 12, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Hsin HU, Sun-Jay CHANG, Jaw-Juinn HORNG, Chung-Hui CHEN
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Publication number: 20130328614Abstract: A band gap reference circuit includes an error-amplifier-based current mirror coupled between a first supply node and a pair of intermediate voltage nodes, and a matched diode pair for providing a proportional-to-absolute temperature (PTAT) current. The matched diode pair includes a first diode connected between a first intermediate voltage node from the pair of intermediate voltage nodes and a second supply node, and a second diode connected in series with a resistor between a second intermediate voltage node from the pair of intermediate voltage nodes and the second supply node. Each diode has a P-N diode junction that is a homojunction.Type: ApplicationFiled: June 12, 2012Publication date: December 12, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jaw-Juinn HORNG, Chung-Hui CHEN, Sun-Jay CHANG, Chia-Hsin HU
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Publication number: 20130270620Abstract: The present disclosure provides one embodiment of a semiconductor structure that includes a semiconductor substrate having a first region and a second region; a shallow trench isolation (STI) feature formed in the semiconductor substrate. The STI feature includes a first portion disposed in the first region and having a first thickness T1 and a second portion disposed in the second region and having a second thickness T2 greater than the first depth, the first portion of the STI feature being recessed from the second portion of the STI feature. The semiconductor structure also includes a plurality of fin active regions on the semiconductor substrate; and a plurality of conductive features disposed on the fin active regions and the STI feature, wherein one of the conductive features covers the first portion of the STI feature in the first region.Type: ApplicationFiled: April 11, 2012Publication date: October 17, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Hsin Hu, Sun-Jay Chang
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Publication number: 20130200455Abstract: A method for performing a stress memorization technique (SMT) a FinFET and a FinFET having memorized stress effects including multi-planar dislocations are disclosed. An exemplary embodiment includes receiving a FinFET precursor with a substrate, a fin structure on the substrate, an isolation region between the fin structures, and a gate stack over a portion of the fin structure. The gate stack separates a source region of the fin structure from a drain region of the fin structure and creates a gate region between the two. The embodiment also includes forming a stress-memorization technique (SMT) capping layer over at least a portion of each of the fin structures, isolation regions, and the gate stack, performing a pre-amorphization implant on the FinFET precursor by implanting an energetic doping species, performing an annealing process on the FinFET precursor, and removing the SMT capping layer.Type: ApplicationFiled: February 8, 2012Publication date: August 8, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wen-Cheng Lo, Sun-Jay Chang
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Patent number: 7897501Abstract: A method of fabricating a semiconductor device is disclosed. The method of fabricating a semiconductor device provides a semiconductor substrate; forming a gate stack overlying the semiconductor substrate; forming spacers each having a first inner spacer and a second outer spacer on sidewalls of the gate stack; forming a protective layer on sidewalls of the spacers, covering a part of the semiconductor substrate, wherein an etching selectivity of the protective layer is higher than that of the first inner spacer.Type: GrantFiled: January 14, 2008Date of Patent: March 1, 2011Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-Li Cheng, Sun-Jay Chang, Tung-Heng Hsieh, Yung-Shen Chen
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Patent number: 7898028Abstract: A process for fabricating a MOSFET device featuring a channel region comprised with a silicon-germanium component is provided. The process features employ an angled ion implantation procedure to place germanium ions in a region of a semiconductor substrate underlying a conductive gate structure. The presence of raised silicon shapes used as a diffusion source for a subsequent heavily-doped source/drain region, the presence of a conductive gate structure, and the removal of dummy insulator previously located on the conductive gate structure allow the angled implantation procedure to place germanium ions in a portion of the semiconductor substrate to be used for the MOSFET channel region. An anneal procedure results in the formation of the desired silicon-germanium component in the portion of semiconductor substrate to be used for the MOSFET channel region.Type: GrantFiled: August 23, 2007Date of Patent: March 1, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sun-Jay Chang, Shien-Yang Wu
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Publication number: 20080268602Abstract: A method of fabricating a semiconductor device is disclosed. The method of fabricating a semiconductor device provides a semiconductor substrate; forming a gate stack overlying the semiconductor substrate; forming spacers each having a first inner spacer and a second outer spacer on sidewalls of the gate stack; forming a protective layer on sidewalls of the spacers, covering a part of the semiconductor substrate, wherein an etching selectivity of the protective layer is higher than that of the first inner spacer.Type: ApplicationFiled: January 14, 2008Publication date: October 30, 2008Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chien-Li Cheng, Sun-Jay Chang, Tung-Heng Hsieh, Yung-Shun Chen
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Publication number: 20070290277Abstract: A process for fabricating a MOSFET device featuring a channel region comprised with a silicon-germanium component is provided. The process features employ an angled ion implantation procedure to place germanium ions in a region of a semiconductor substrate underlying a conductive gate structure. The presence of raised silicon shapes used as a diffusion source for a subsequent heavily-doped source/drain region, the presence of a conductive gate structure, and the removal of dummy insulator previously located on the conductive gate structure allow the angled implantation procedure to place germanium ions in a portion of the semiconductor substrate to be used for the MOSFET channel region. An anneal procedure results in the formation of the desired silicon-germanium component in the portion of semiconductor substrate to be used for the MOSFET channel region.Type: ApplicationFiled: August 23, 2007Publication date: December 20, 2007Inventors: Sun-Jay Chang, Shien-Yang Wu
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Patent number: 7279430Abstract: A process for fabricating a MOSFET device featuring a channel region comprised with a silicon-germanium component is provided. The process features employ an angled ion implantation procedure to place germanium ions in a region of a semiconductor substrate underlying a conductive gate structure. The presence of raised silicon shapes used as a diffusion source for a subsequent heavily doped source/drain region, the presence of a conductive gate structure, and the removal of dummy insulator previously located on the conductive gate structure allow the angled implantation procedure to place germanium ions in a portion of the semiconductor substrate to be used for the MOSFET channel region. An anneal procedure results in the formation of the desired silicon-germanium component in the portion of semiconductor substrate to be used for the MOSFET channel region.Type: GrantFiled: August 17, 2004Date of Patent: October 9, 2007Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sun-Jay Chang, Shien-Yang Wu
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Patent number: 7220630Abstract: A strained channel MOSFET device with improved charge carrier mobility and method for forming the same, the method including providing a first and second FET device having a respective first polarity and second polarity opposite the first polarity on a substrate; forming a strained layer having a stress selected from the group consisting of compressive and tensile on the first and second FET devices; and, removing a thickness portion of the strained layer over one of the first and second FET devices to improve charge carrier mobility.Type: GrantFiled: May 21, 2004Date of Patent: May 22, 2007Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kaun-Lun Cheng, Shui-Ming Cheng, Yu-Yuan Yao, Ka-Hing Fung, Sun-Jay Chang
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Patent number: 7190033Abstract: A CMOS device and manufacturing method thereof wherein a bilayer etch stop is used over a PMOS transistor, and a single etch stop layer is used for an NMOS transistor, for forming contacts to the source or drain of the CMOS device. A surface tension-reducing layer is disposed between the source or drain region of the PMOS transistor and an overlying surface tension-inducing layer. The surface tension-inducing layer may comprise a nitride material or carbon-containing material, and the surface tension-reducing layer may comprise an oxide material. Degradation of hole mobility in the PMOS transistor is prevented by the use of the surface tension-reducing layer of the bilayer etch stop.Type: GrantFiled: April 15, 2004Date of Patent: March 13, 2007Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sun-Jay Chang, Chien-Li Cheng
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Patent number: 7078723Abstract: A microelectronic device includes a substrate, and a patterned feature located over the substrate and a plurality of doped regions, wherein the patterned feature includes at least one electrode. The microelectronic device includes at least one sill region for the enhancement of electron and/or hole mobility.Type: GrantFiled: April 6, 2004Date of Patent: July 18, 2006Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chuan-Yi Lin, Wen-Chin Lee, Sun-Jay Chang, Shien-Yang Wu
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Publication number: 20060040503Abstract: A process for fabricating a MOSFET device featuring a channel region comprised with a silicon-germanium component is provided. The process features employ an angled ion implantation procedure to place germanium ions in a region of a semiconductor substrate underlying a conductive gate structure. The presence of raised silicon shapes used as a diffusion source for a subsequent heavily doped source/drain region, the presence of a conductive gate structure, and the removal of dummy insulator previously located on the conductive gate structure allow the angled implantation procedure to place germanium ions in a portion of the semiconductor substrate to be used for the MOSFET channel region. An anneal procedure results in the formation of the desired silicon-germanium component in the portion of semiconductor substrate to be used for the MOSFET channel region.Type: ApplicationFiled: August 17, 2004Publication date: February 23, 2006Inventors: Sun-Jay Chang, Shien-Yang Wu
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Publication number: 20050260810Abstract: A strained channel MOSFET device with improved charge carrier mobility and method for forming the same, the method including providing a first and second FET device having a respective first polarity and second polarity opposite the first polarity on a substrate; forming a strained layer having a stress selected from the group consisting of compressive and tensile on the first and second FET devices; and, removing a thickness portion of the strained layer over one of the first and second FET devices to improve charge carrier mobility.Type: ApplicationFiled: May 21, 2004Publication date: November 24, 2005Inventors: Kaun-Lun Cheng, Shui-Ming Cheng, Yu-Yuan Yao, Ka-Hing Fung, Sun-Jay Chang
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Publication number: 20050230756Abstract: A CMOS device and manufacturing method thereof wherein a bilayer etch stop is used over a PMOS transistor, and a single etch stop layer is used for an NMOS transistor, for forming contacts to the source or drain of the CMOS device. A surface tension-reducing layer is disposed between the source or drain region of the PMOS transistor and an overlying surface tension-inducing layer. The surface tension-inducing layer may comprise a nitride material or carbon-containing material, and the surface tension-reducing layer may comprise an oxide material. Degradation of hole mobility in the PMOS transistor is prevented by the use of the surface tension-reducing layer of the bilayer etch stop.Type: ApplicationFiled: April 15, 2004Publication date: October 20, 2005Inventors: Sun-Jay Chang, Chien-Li Cheng