Abstract: A method includes receiving feature data defining a plurality of features of a virtual substrate. The method further includes preparing the virtual substrate for display on a graphical user interface (GUI). The method further includes receiving one or more first inputs via the GUI. The one or more first inputs are associated with one or more locations of the virtual substrate. The method further includes defining a three-dimensional measurement probe based on the one or more first inputs. The method further includes outputting a measurement of the measurement probe. The measurement is associated with a characteristic of the virtual substrate measured by the three-dimensional measurement probe.

Abstract: A two-terminal resistive switching device (TTRSD) such as a non-volatile two-terminal memory device or a volatile two-terminal selector device can be formed according to a manufacturing process. The process can include forming an etch stop layer that is made of aluminum and can include forming a buffer layer below the etch stop layer and/or between the etch stop layer and a top electrode of the TTRSD.

Abstract: A method includes receiving profile data of a plurality of features of a substrate. The method further includes generating a typical profile based on the profile data of the plurality of features. The method further includes generating a first array of features. Each of the first array of features is based on the typical profile. The method further includes providing the first array of features to a process model. The method further includes obtaining first output from the process model based on the first array of features. The method further includes causing performance of a corrective action in view of the first output from the process model.

Abstract: A self-aligned memory device includes a conductive bottom plug disposed within an insulating layer and having a coplanar top surface, a self-aligned planar bottom electrode disposed upon the coplanar top surface and having a thickness within a range of 50 Angstroms to 200 Angstroms, a planar switching material layer disposed upon the self-aligned planar bottom electrode, a planar active metal material layer disposed upon the planar switching material layer and a planar top electrode disposed above the planar active metal material layer, wherein the self-aligned planar bottom electrode, the planar switching material layer, the planar active metal material layer, and the planar top electrode form a pillar-like structure above the insulating layer.

Abstract: Two-terminal resistive switching devices can have a switching layer in which a filament forms and deforms to varying degrees to represent distinct logical states. This switching layer can be formed having a varying ratio, X, of nitrogen to silicon at various strata of the switching layer. Such can result in a two-terminal memory device with improved stability and other characteristics.

Abstract: Resistive switching memory cells having filament-based switching mechanisms are provided. By way of example, resistive switching memory cells having resistive filaments constrained to a core of the cell are disclosed. In other examples, methods for fabricating resistive switching memory cells to constrain a conductive filament formed in the resistive switching memory cell to a central portion of core of the cell are disclosed.

Abstract: Fabrication of resistive switching memory devices is herein provided. By way of example, a method for a two-step etch for fabricating a non-volatile resistive memory device is disclosed. In another example, a method for a three-step etch for fabricating a non-volatile resistive memory device is provided. Still other embodiments disclose a method for fabricating a non-volatile metal nitrogen/metal oxygen resistive switching memory device. Further embodiments disclose a method for fabricating a volatile resistive switching selector device. Processes for forming protective spacers in conjunction with fabricating a disclosed resistive memory device are also provided.

Abstract: A two-terminal resistive switching device (TTRSD) such as a non-volatile two-terminal memory device or a volatile two-terminal selector device can be formed according to a manufacturing process. The process can include forming an etch stop layer that is made of aluminum and can include forming a buffer layer below the etch stop layer and/or between the etch stop layer and a top electrode of the TTRSD.

Abstract: A two-terminal resistive switching device (TTRSD) such as a non-volatile two-terminal memory device or a volatile two-terminal selector device can be formed according to a manufacturing process. The process can include forming an etch stop layer that is made of aluminum and can include forming a buffer layer below the etch stop layer and/or between the etch stop layer and a top electrode of the TTRSD.

Abstract: Two-terminal memory devices can be formed in dielectric material that is electrically insulating and operates as a blocking layer to mitigate diffusion of material from a metal layer. A stack of layers of the two-terminal memory device can be covered with a liner layer that can comprise the dielectric material. Thus, in some implementations, the liner layer and the blocking layer can have a similar etch rate.

Abstract: A self-aligned memory device includes a conductive bottom plug disposed within an insulating layer and having a coplanar top surface, a self-aligned planar bottom electrode disposed upon the coplanar top surface and having a thickness within a range of 50 Angstroms to 200 Angstroms, a planar switching material layer disposed upon the self-aligned planar bottom electrode, a planar active metal material layer disposed upon the planar switching material layer and a planar top electrode disposed above the planar active metal material layer, wherein the self-aligned planar bottom electrode, the planar switching material layer, the planar active metal material layer, and the planar top electrode form a pillar-like structure above the insulating layer.

Abstract: Provision of fabrication, construction, and/or assembly of a two-terminal memory device is described herein. The two-terminal memory device can include an active region with a silicon bearing layer, an interface layer, and an active metal layer. The interface layer can be grown on the silicon bearing layer, and the growth of the interface layer can be regulated with N2O plasma.

Abstract: Two-terminal memory devices can be formed in part within a dielectric material that is electrically insulating and operates as a blocking layer to mitigate diffusion of metal particles employed in integrated circuit fabrication. This dielectric material can be protected from other fabrication processes corrosive to the dielectric material (e.g., CMP, HF clean, etc) by a silicon containing liner. Use of the silicon containing liner can enable a minimum thickness of the dielectric material to be preserved and can facilitate step height differences between adjacent material surfaces that form a two-terminal memory device to be on the order of less than about five angstroms. This small step height difference, particularly when underlying a switching layer of the two-terminal memory device, can yield excellent switching characteristics.

Abstract: Providing for a memory device having a resistive switching memory integrated within backend layers of the memory device is described herein. By way of example, the resistive switching memory can be embedded memory such as cache, random access memory, or the like, in various embodiments. The resistive memory can be fabricated between various backend metallization schemes, including backend copper metal layers and in part utilizing one or more damascene processes. In some embodiments, the resistive memory can be fabricated in part with damascene processes and in part with subtractive etch processing, utilizing four or fewer photo-resist masks. Accordingly, the disclosure provides a relatively low cost, high performance embedded memory compatible with a variety of fabrication processes of integrated circuit foundries.

Abstract: A memory cell that includes a first metal layer formed over a substrate is provided. The substrate includes one or more complementary metal-oxide semiconductor devices. The memory cell also includes a via device that connects at least a portion of the first metal layer and at least another portion of a second metal layer. The first metal layer has a first thickness having an edge thereof that serves as an electrode for a memory cell formed by the via device. The memory cell scales as a function of the first thickness and at least in part independent of a minimum feature size of the memory device.

Abstract: A recessed high voltage metal oxide semiconductor (MOS) transistor is provided for use in a two-terminal memory cell. The two-terminal memory cell can include a resistive switching device connected to the recessed MOS transistor. The recessed MOS transistor provides for an increased channel length relative to the transistor size in comparison to a traditional MOS transistor. This allows for a decreased memory cell size while maintaining comparable electrical parameters (threshold voltage, channel length, and leakage) than would otherwise be possible. The recessed MOS transistor can be made as either a NMOS or PMOS device using n-type or p-type materials respectively, where the channel, or inversion layer, is formed by electrons (NMOS) or holes (PMOS) between the source and drain in the transistor.

Abstract: Provided is a monolithic integration of resistive memory with complementary metal oxide semiconductor using integrated circuit foundry processes. A memory device is provided that includes a substrate comprising one or more complementary metal-oxide semiconductor devices, a first insulator layer formed on the substrate; and a monolithic stack. The monolithic stack includes multiple layers fabricated as part of a monolithic process over the first insulator layer. The multiple layers include a first metal layer, a second insulator layer, and a second metal layer. A resistive memory device structure is formed within the second insulator layer and within a thermal budget of the one or more complementary metal-oxide semiconductor devices. The resistive memory device structure is implemented as a pillar device or as a via device. Further, the first metal layer is coupled to the second metal layer.

Abstract: A two-terminal memory device can be formed according to a manufacturing process that utilizes two distinct chemical-mechanical planarization (CMP) processes for each of bottom electrode/terminal (BE) and the top electrode/terminal (TE). The CMP processes can reduce planar height variations for a top surface of the BE and a top surface of the TE. The CMP processes can reduce height differences between the top surface of the BE and adjacent dielectric surfaces and reduce height differences between the top surface of the TE and adjacent dielectric surfaces.

Abstract: Two-terminal memory devices can be formed in part within a dielectric material that is electrically insulating and operates as a blocking layer to mitigate diffusion of metal particles employed in integrated circuit fabrication. This dielectric material can be protected from other fabrication processes corrosive to the dielectric material (e.g., CMP, HF clean, etc) by a silicon containing liner. Use of the silicon containing liner can enable a minimum thickness of the dielectric material to be preserved and can facilitate step height differences between adjacent material surfaces that form a two-terminal memory device to be on the order of less than about five angstroms. This small step height difference, particularly when underlying a switching layer of the two-terminal memory device, can yield excellent switching characteristics.

Abstract: A two-terminal resistive switching device (TTRSD) such as a non-volatile two-terminal memory device or a volatile two-terminal selector device can be formed according to a manufacturing process. The process can include forming an etch stop layer comprising aluminum and can include forming a buffer layer below the etch stop layer and/or between the etch stop layer and a top electrode of the TTRSD.