Abstract: A method of making a semiconductor structure includes trimming a patterned hard mask with a wet etch, wherein the hard mask is on a gate layer; and etching the gate layer. In making multiple structures on a semiconductor wafer, an average width of lines in the patterned hard mask is trimmed by at least 100 ?.

Abstract: A method of forming a semiconductor structure comprises forming an etch-stop layer comprising nitride, on a stack. The stack is on a semiconductor substrate, and the stack comprises (i) a gate layer. The forming is by CVD with a gas comprising a first compound which is SixL2x, and a second compound comprising nitrogen and deuterium, L is an amino group, and X is 1 or 2.

Abstract: A method is provided for determining a concentration profile of an impurity within a layer of a semiconductor topography. The method may include exposing the layer and an underlying layer to oxidizing conditions. In addition, the method may include comparing thickness measurements of total dielectric above the underlying layer taken before and after exposing the topography to oxidizing conditions . In some cases, the comparison may include plotting pre-oxidation thickness measurements versus post-oxidation measurements. In other embodiments, the comparison may include determining differences between the pre-oxidation and post-oxidation thickness measurements and correlating the differences to concentrations of the impurity. In some cases, such a correlation may include subtracting a concentration of the impurity at a first location along the semiconductor topography from a concentration of the impurity at a second location along the semiconductor topography.

Abstract: A method of making a semiconductor structure comprises forming an oxide layer on a substrate; forming a silicon nitride layer on the oxide layer; annealing the layers in NO; and annealing the layers in ammonia. The equivalent oxide thickness of the oxide layer and the silicon nitride layer together is at most 25 Angstroms.

Abstract: A method of nitriding a gate oxide layer by annealing a preformed oxide layer with nitric oxide (NO) gas is disclosed. The nitridation process can be carried out at lower temperatures and pressures than a conventional nitrous oxide anneal while still achieving acceptable levels of nitridation. The nitridation process can be conducted at atmospheric or sub-atmospheric pressures. As a result, the nitridation process can be used to form nitrided gate oxide layers in-situ in a CVD furnace. The nitrided gate oxide layer can optionally be reoxidized in a second oxidation step after the nitridation step. A gate electrode layer (e.g., boron doped polysilicon) can then be deposited on top of the nitrided gate oxide layer or on top of the reoxidized and nitrided gate oxide layer.

Abstract: A method of forming a semiconductor structure comprises forming a nitride layer on a stack, and etching the nitride layer to form spacers in contact with sides of the stack. The stack is on a semiconductor substrate, the stack comprises (i) a gate layer, comprising silicon, (ii) a metallic layer, on the gate layer, and (iii) an etch-stop layer, on the metallic layer. The forming is by CVD with a gas comprising SixL2x, L is an amino group, and X is 1 or 2.

Abstract: A method is provided which includes forming a deep isolation structure within a semiconductor topography. In some cases, the method may include forming a first isolation structure within a semiconductor layer and etching an opening within the isolation structure to expose the semiconductor layer. In addition, the method may include etching the semiconductor layer to form a trench extending through the isolation structure and at least part of the semiconductor layer. In some cases, the method may include removing part of a first fill layer deposited within the trench such that an upper surface of the fill layer is below an upper portion of the trench. In such an embodiment, the vacant portion of the trench may be filled with a second fill layer. In yet other embodiments, the method may include planarizing the first fill layer within the trench and subsequently oxidizing an upper portion of the fill layer.

Abstract: An improved furnace system and method is provided to substantially minimize, if not eliminate, ambient air from entering a heated chamber of the furnace system during a critical processing step. The furnace system can be used in, for example, an oxidation step where ambient air containing oxygen is prevented from entering an atmospheric pressure tube by essentially purging potential leak areas with an inert gas, such as nitrogen, at the critical moment during temperature ramp up and ramp down, and prior to temperature stabilization and the introduction of an oxidizing gas. If oxygen is not present within the tube, then a tungsten sidewall surface of a gate conductor, for example, will not inadvertently oxidize at the critical pre- and post-oxidation moments. However, if steam is present where hydrogen is available with oxygen, the underlying polysilicon sidewall surface will selectively oxidize instead of the overlying tungsten.

Abstract: In one embodiment, a transistor is fabricated by forming gate materials, such as a gate oxide layer and a gate polysilicon layer, prior to forming a shallow trench isolation (STI) structure. Forming the gate materials early in the process minimizes exposure of the STI structure to processing steps that may expose its corners. Also, to minimize cross-diffusion of dopants and to help lower gate resistance, a metal stack comprising a barrier layer and a metal layer may be employed as a conductive line between gates. In one embodiment, the metal stack comprises a barrier layer of tungsten-nitride and a metal layer of tungsten.

Abstract: A method and a structure are provided for measuring a concentration of an impurity within a layer arranged upon a semiconductor substrate. The method may include exposing the layer and semiconductor substrate to oxidizing conditions and determining a difference in total dielectric thickness above the substrate from before to after exposing the layer and substrate. The difference may be correlated to a concentration of the impurity. In some cases, the method may include designating a plurality of measurement locations on the layer such that a concentration profile of the impurity within the layer may be determined. In some embodiments, exposing the layer and substrate may include forming an oxidized interface between the layer and the semiconductor substrate. Preferably, the oxidized interface is thicker underneath portions of the layer with a lower concentration of the impurity than underneath portions of the layer with a higher concentration of the impurity.

Abstract: A method of nitriding a gate oxide layer by annealing a preformed oxide layer with nitric oxide (NO) gas is disclosed. The nitridation process can be carried out at lower temperatures and pressures than a conventional nitrous oxide anneal while still achieving acceptable levels of nitridation. The nitridation process can be conducted at atmospheric or sub-atmospheric pressures. As a result, the nitridation process can be used to form nitrided gate oxide layers in-situ in a CVD furnace. The nitrided gate oxide layer can optionally be reoxidized in a second oxidation step after the nitridation step. A gate electrode layer (e.g., boron doped polysilicon) can then be deposited on top of the nitrided gate oxide layer or on top of the reoxidized and nitrided gate oxide layer.

Abstract: A method of determining the nitrogen content of a nitrided gate oxide layer on a semiconductor substrate is provided. The method comprises steps of: oxidizing the nitrided gate oxide layer; measuring the thickness of the oxidized nitrided gate oxide layer; optionally determining the change in thickness of the oxidized nitrided gate oxide layer; and determining if the measured thickness or calculated change in thickness exceeds a predetermined level. The oxidizing step may be conducted in a conventional furnace or in a rapid thermal processing (RTP) chamber. In a preferred embodiment of the invention, the method further comprises measuring the thickness of the oxidized nitrided gate oxide layer for a plurality of samples having known nitrogen contents and performing a least squares regression analysis on the data to generate a calibration curve for nitrogen content as a function of oxidized nitrided gate oxide thickness.