Patents by Inventor Sundarrajan Rangachari
Sundarrajan Rangachari has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200177417Abstract: An electrical system includes a transceiver with an IQ estimator and an IQ mismatch corrector. The electrical system also includes an antenna coupled to the transceiver. The IQ estimator is configured to perform frequency-domain IQ mismatch analysis to determine an IQ mismatch estimate at available frequency bins of a baseband data signal. The IQ mismatch corrector is configured to correct the baseband data signal based on the IQ mismatch estimate.Type: ApplicationFiled: November 26, 2019Publication date: June 4, 2020Inventors: Jawaharlal TANGUDU, Sashidharan VENKATRAMAN, Sundarrajan RANGACHARI, Sarma Sundareswara GUNTURI, Sthanunathan RAMAKRISHNAN
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Publication number: 20200162083Abstract: A method for dithering a fractional clock divider includes generating a first clock enable sequence based on a seed pattern of M ones and N minus M zeros, selecting a cyclic rotation of the seed pattern after N input clock cycles, and generating a second clock enable sequence based on the cyclic rotation. A clock gate receives the input clock signal and the clock enable sequences and outputs M clock cycles for every N input clock cycles. A random number generator indicates the cyclic rotation of the seed pattern. The seed pattern can be replaced with an updated seed pattern of M ones and N minus M zeros in a different order. In some examples, the clock enable sequence is generated using a cyclic shift register containing the seed pattern and a multiplexor. In other examples, the clock enable sequence is generated using a modulo N counter and a comparator.Type: ApplicationFiled: February 6, 2019Publication date: May 21, 2020Inventors: Sundarrajan RANGACHARI, Sriram MURALI, Sanjay PENNAM
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Publication number: 20200153444Abstract: A digital clock generator for a digital clock domain interfaced to another clock domain through a FIFO, includes division selector circuitry to provide an input randomizing sequence of clock division factors, selected from a defined set of clock division factors corresponding to a target average clock division, and division arbitration circuitry to generate a drift-corrected randomizing sequence of clock division factors, based at least in part on the input randomizing sequence of clock division factors, and an accumulated drift correction signal. A clock drift control loop generates the accumulated drift correction signal, based at least in part on an accumulated clock drift relative to the target average clock division. Clock generation can be based on randomized division with the drift-corrected randomizing sequence of clock division factors. The drift-corrected randomizing sequence of clock division factors can be generated so that clock drift is bounded based on a FIFO depth.Type: ApplicationFiled: November 11, 2019Publication date: May 14, 2020Inventors: Sarma Sundareswara Gunturi, Jawaharlal Tangudu, Sundarrajan Rangachari
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Patent number: 10651836Abstract: A clock generator circuit includes a clock divider circuit, a clock pulse control circuit, a phase shifter circuit, and a clock multiplexer circuit. The clock divider circuit is configured to generate a divided clock having a frequency that is a programmable fraction of a frequency of an input clock. The clock pulse control circuit is coupled to the clock divider circuit, and is configured to generate a pulse shaped clock that includes a clock burst comprising a programmable number of adjacent cycles of the divided clock. The phase shifter circuit is coupled to the clock control circuit, and is configured to generate a plurality of phase shifted clocks. Each of phase shifted clocks is a differently delayed version of the pulse shaped clock. The clock multiplexer circuit is coupled to the phase shifter circuit, and is configured to selectively route each of the phase shifted clocks to an output terminal.Type: GrantFiled: February 21, 2019Date of Patent: May 12, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Gautam Sanjay Kale, Sundarrajan Rangachari, Nagalinga Swamy Basayya Aremallapur
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Patent number: 10651863Abstract: A method for dithering a fractional clock divider includes generating a first clock enable sequence based on a seed pattern of M ones and N minus M zeros, selecting a cyclic rotation of the seed pattern after N input clock cycles, and generating a second clock enable sequence based on the cyclic rotation. A clock gate receives the input clock signal and the clock enable sequences and outputs M clock cycles for every N input clock cycles. A random number generator indicates the cyclic rotation of the seed pattern. The seed pattern can be replaced with an updated seed pattern of M ones and N minus M zeros in a different order. In some examples, the clock enable sequence is generated using a cyclic shift register containing the seed pattern and a multiplexor. In other examples, the clock enable sequence is generated using a modulo N counter and a comparator.Type: GrantFiled: February 6, 2019Date of Patent: May 12, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sundarrajan Rangachari, Sriram Murali, Sanjay Pennam
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Patent number: 10574246Abstract: A digital local oscillator includes a look-up table and oscillator control circuitry. The look-up table contains samples of the digital local oscillator signal. The oscillator control circuitry is configured to select samples from the look-up table based on an accumulated phase value. The oscillator control circuitry is also configured to add a correction value to the accumulated phase value based on a difference of a frequency of the digital local oscillator signal and a desired frequency.Type: GrantFiled: April 10, 2018Date of Patent: February 25, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sarma Sundareswara Gunturi, Sundarrajan Rangachari, Aswath Vs, Raunak Dhaniwala
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Patent number: 10396829Abstract: A digital filter for interpolation or decimation and a device incorporating the digital filter is disclosed. The digital filter includes a filter block, a first transformation circuit coupled to the filter block and an input stream coupled to provide input values to a component selected from the filter block and the first transformation circuit. The filter block includes a pair of sub-filters having respective transformed coefficients, the respective transformed coefficients of a first sub-filter of the pair of sub-filters being symmetric and the respective transformed coefficients of a second sub-filter of the pair of sub-filters being anti-symmetric. The first transformation circuit is coupled to perform a first transformation; the filter block and the first transformation circuit together provide suppression of undesired spectral images in final outputs of the digital filter.Type: GrantFiled: August 23, 2018Date of Patent: August 27, 2019Assignee: TEXAS INTSTUMENTS INCORPORATEDInventors: Jaiganesh Balakrishnan, Suvam Nandi, Sundarrajan Rangachari
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Publication number: 20190207612Abstract: A digital local oscillator includes a look-up table and oscillator control circuitry. The look-up table contains samples of the digital local oscillator signal. The oscillator control circuitry is configured to select samples from the look-up table based on an accumulated phase value. The oscillator control circuitry is also configured to add a correction value to the accumulated phase value based on a difference of a frequency of the digital local oscillator signal and a desired frequency.Type: ApplicationFiled: April 10, 2018Publication date: July 4, 2019Inventors: Sarma Sundareswara GUNTURI, Sundarrajan RANGACHARI, Aswath VS, Raunak DHANIWALA
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Publication number: 20190204387Abstract: A circuit includes a test circuit in an integrated circuit to test signal timing of a logic circuit under test in the integrated circuit. The signal timing includes timing measurements to determine if an output of the logic circuit under test changes state in response to a clock signal. The test circuit includes a bit register that specifies which bits of the logic circuit under test are to be tested in response to the clock signal. A configuration register specifies a selected clock source setting from multiple clock source settings corresponding to a signal speed. The selected clock source is employed to perform the timing measurements of the specified bits of the bit register.Type: ApplicationFiled: December 14, 2018Publication date: July 4, 2019Inventors: PRAKASH NARAYANAN, SUNDARRAJAN RANGACHARI, PRASHANTH SARAF
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Publication number: 20190181842Abstract: In some embodiments, a multiplier-based programmable filter comprises a pre-scaling circuit, a first multiplier circuit coupled to a first output of the pre-scaling circuit and a second output of the pre-scaling circuit, and a second multiplier circuit coupled to the first output of the pre-scaling circuit and the second output of the pre-scaling circuit. In some embodiments, the multiplier-based programmable filter also comprises a first adder coupled to a first output of the first multiplier circuit and a second output of the first multiplier circuit, a second adder coupled to a first output of the second multiplier circuit and a second output of the second multiplier circuit, first register coupled to an output of the first adder and an input of the second adder, and a second register coupled to an output of the second adder.Type: ApplicationFiled: December 12, 2017Publication date: June 13, 2019Inventors: Sundarrajan RANGACHARI, Jaiganesh BALAKRISHNAN, Jawaharlal TANGUDU, Srinivas Kumar Reddy NARU
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Patent number: 10320412Abstract: Disclosed embodiments include a system having a first memory, a second memory, circuitry that reads data quantities from the first memory along a first orientation, a compression engine that compresses each of the read data quantities to produce corresponding compressed data quantities, and circuitry that writes the compressed data quantities to the second memory along a second orientation which differs from the first orientation. The read data quantities have a first bit width and the compressed data quantities have a second bit width that is less than the first bit width.Type: GrantFiled: February 13, 2018Date of Patent: June 11, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sundarrajan Rangachari, Desmond Pravin Martin Fernandes, Rakesh Channabasappa Yaraduyathinahalli
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Patent number: 10305451Abstract: In some embodiments, a multiplier-based programmable filter comprises a pre-scaling circuit, a first multiplier circuit coupled to a first output of the pre-scaling circuit and a second output of the pre-scaling circuit, and a second multiplier circuit coupled to the first output of the pre-scaling circuit and the second output of the pre-scaling circuit. In some embodiments, the multiplier-based programmable filter also comprises a first adder coupled to a first output of the first multiplier circuit and a second output of the first multiplier circuit, a second adder coupled to a first output of the second multiplier circuit and a second output of the second multiplier circuit, first register coupled to an output of the first adder and an input of the second adder, and a second register coupled to an output of the second adder.Type: GrantFiled: December 12, 2017Date of Patent: May 28, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sundarrajan Rangachari, Jaiganesh Balakrishnan, Jawaharlal Tangudu, Srinivas Kumar Reddy Naru
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Publication number: 20180367169Abstract: A digital filter for interpolation or decimation and a device incorporating the digital filter is disclosed. The digital filter includes a filter block, a first transformation circuit coupled to the filter block and an input stream coupled to provide input values to a component selected from the filter block and the first transformation circuit. The filter block includes a pair of sub-filters having respective transformed coefficients, the respective transformed coefficients of a first sub-filter of the pair of sub-filters being symmetric and the respective transformed coefficients of a second sub-filter of the pair of sub-filters being anti-symmetric. The first transformation circuit is coupled to perform a first transformation; the filter block and the first transformation circuit together provide suppression of undesired spectral images in final outputs of the digital filter.Type: ApplicationFiled: August 23, 2018Publication date: December 20, 2018Inventors: Jaiganesh Balakrishnan, Suvam Nandi, Sundarrajan Rangachari
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Patent number: 10090866Abstract: A digital filter for interpolation or decimation and a device incorporating the digital filter is disclosed. The digital filter includes a filter block, a first transformation circuit coupled to the filter block and an input stream coupled to provide input values to a component selected from the filter block and the first transformation circuit. The filter block includes a pair of sub-filters having respective transformed coefficients, the respective transformed coefficients of a first sub-filter of the pair of sub-filters being symmetric and the respective transformed coefficients of a second sub-filter of the pair of sub-filters being anti-symmetric. The first transformation circuit is coupled to perform a first transformation; the filter block and the first transformation circuit together provide suppression of undesired spectral images in final outputs of the digital filter.Type: GrantFiled: December 30, 2016Date of Patent: October 2, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jaiganesh Balakrishnan, Suvam Nandi, Sundarrajan Rangachari
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Publication number: 20180252771Abstract: Methods and apparatus for self test of safety logic in safety critical devices is provided in which the safety logic includes comparator logic coupled to a circuit under test (CUT) in a safety critical device and the self test logic is configured to test the comparator logic. The self test logic may be implemented as a single cycle parallel bit inversion approach, a multi-cycle serial bit inversion approach, or a single cycle test pattern injection approach.Type: ApplicationFiled: May 7, 2018Publication date: September 6, 2018Inventors: Sundarrajan Rangachari, Saket Jalan
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Publication number: 20180191383Abstract: A digital filter for interpolation or decimation and a device incorporating the digital filter is disclosed. The digital filter includes a filter block, a first transformation circuit coupled to the filter block and an input stream coupled to provide input values to a component selected from the filter block and the first transformation circuit. The filter block includes a pair of sub-filters having respective transformed coefficients, the respective transformed coefficients of a first sub-filter of the pair of sub-filters being symmetric and the respective transformed coefficients of a second sub-filter of the pair of sub-filters being anti-symmetric. The first transformation circuit is coupled to perform a first transformation; the filter block and the first transformation circuit together provide suppression of undesired spectral images in final outputs of the digital filter.Type: ApplicationFiled: December 30, 2016Publication date: July 5, 2018Inventors: Jaiganesh Balakrishnan, Suvam Nandi, Sundarrajan Rangachari
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Publication number: 20180175880Abstract: Disclosed embodiments include a system having a first memory, a second memory, circuitry that reads data quantities from the first memory along a first orientation, a compression engine that compresses each of the read data quantities to produce corresponding compressed data quantities, and circuitry that writes the compressed data quantities to the second memory along a second orientation which differs from the first orientation. The read data quantities have a first bit width and the compressed data quantities have a second bit width that is less than the first bit width.Type: ApplicationFiled: February 13, 2018Publication date: June 21, 2018Inventors: Sundarrajan RANGACHARI, Desmond Pravin Martin FERNANDES, Rakesh Channabasappa Yaraduyathinahalli
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Patent number: 9964597Abstract: Methods and apparatus for self test of safety logic in safety critical devices is provided in which the safety logic includes comparator logic coupled to a circuit under test (CUT) in a safety critical device and the self test logic is configured to test the comparator logic. The self test logic may be implemented as a single cycle parallel bit inversion approach, a multi-cycle serial bit inversion approach, or a single cycle test pattern injection approach.Type: GrantFiled: September 1, 2016Date of Patent: May 8, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sundarrajan Rangachari, Saket Jalan
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Patent number: 9929744Abstract: Disclosed embodiments include a system having a first memory for storing a plurality of data quantities, each data quantity consisting of a first number of bits, and a second memory for storing a plurality of compressed data quantities, each compressed data quantity consisting of a second number of bits that is less than the first number of bits. The system includes circuitry for reading data quantities from the first memory and for writing compressed data quantities, corresponding to respective read data quantities, to non-sequential addresses in the second memory. The circuitry for reading data quantities from the first memory is for reading along a read orientation selected from one of row-orientation or column-orientation from the first memory, and the circuitry for writing compressed data quantities in the second memory is for writing along a write orientation in the second memory that differs from the read orientation.Type: GrantFiled: October 12, 2017Date of Patent: March 27, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sundarrajan Rangachari, Desmond Pravin Martin Fernandes, Rakesh Channabasappa Yaraduyathinahalli
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Publication number: 20180059180Abstract: Methods and apparatus for self test of safety logic in safety critical devices is provided in which the safety logic includes comparator logic coupled to a circuit under test (CUT) in a safety critical device and the self test logic is configured to test the comparator logic. The self test logic may be implemented as a single cycle parallel bit inversion approach, a multi-cycle serial bit inversion approach, or a single cycle test pattern injection approach.Type: ApplicationFiled: September 1, 2016Publication date: March 1, 2018Inventors: Sundarrajan Rangachari, Saket Jalan