Abstract: Disclosed embodiments include a system having a first memory for storing a plurality of data quantities, each data quantity consisting of a first number of bits, and a second memory for storing a plurality of compressed data quantities, each compressed data quantity consisting of a second number of bits that is less than the first number of bits. The system includes circuitry for reading data quantities from the first memory and for writing compressed data quantities, corresponding to respective read data quantities, to non-sequential addresses in the second memory. The circuitry for reading data quantities from the first memory is for reading along a read orientation selected from one of row-orientation or column-orientation from the first memory, and the circuitry for writing compressed data quantities in the second memory is for writing along a write orientation in the second memory that differs from the read orientation.

Abstract: A digital data storage and retrieval system. The system has a first memory for storing a plurality of data quantities, and each data quantity, in the plurality of data quantities, consists of a first number of bits. The system also has a second memory for storing a plurality of compressed data quantities, and each compressed data quantity, in the plurality of compressed data quantities, consists of a second number of bits that is less than the first number of bits. The system also has circuitry for reading data quantities from the first memory and circuitry for writing compressed data quantities, corresponding to respective read data quantities, to non-sequential addresses in the second memory. The system also may include circuitry for reading compressed data quantities from the second memory, and circuitry for writing decompressed data quantities, corresponding to respective read compressed data quantities, to non-sequential addresses in the first memory.

Abstract: A weather band receiver, which may be part of an FM receiver, is disclosed. FSK-encoded data units in an alert packet transmission are detected using a quadrature matched filter circuit. At least one FSK-encoded data unit is captured from the alert packet transmission. Soft quantized bits are extracted from the FSK-encoded data units. The soft quantized bits are saved to memory and used to recover an alert message. Soft quantized bits from two or more FSK-encoded data units may be combined before recovering the alert message.

Abstract: Example embodiments of the systems and methods of variable fractional rate digital resampling as disclosed herein achieve variable rate conversion. In the example embodiments, the input samples are upsampled by a factor N in an upsampler followed by a filter which then goes through a linear interpolator. The filter cleans the spectral images of the signal created due to the upsampling operation.

Abstract: Example embodiments of systems and methods of direct oversampled low PAR pulse shaping encapsulating DSSS spreading are disclosed herein. Pulse-shaping of a DSSS spread data symbol stream results in a small number of waveform patterns to choose from for any data-symbol window. Low complexity programmable look-up table (LUT) based direct pulse shaping may be implemented, while only needing to compute a negation function. The chosen pulse shape may generate a low PAR for the baseband signal, allowing for a reduction in the saturation power of the power amplifier, thereby reducing the overall transmitter power consumption.

Abstract: Example embodiments of the systems and methods of variable fractional rate digital resampling as disclosed herein achieve variable rate conversion. In the example embodiments, the input samples are upsampled by a factor N in an upsampler followed by a filter which then goes through a linear interpolator. The filter cleans the spectral images of the signal created due to the upsampling operation.

Abstract: Example embodiments of the systems and methods of low power decimation filter exploit the single bit data input to the filter and the symmetry of the filter response. The input data may be treated as 0 and 1 instead of ?1 and +1. The symmetry of the sinc filter may be exploited since the data across different polyphases are combined. The addition of the symmetric data and coefficient multiplication may be replaced with simple muxing based on two bits and the use of unsigned logic for all adders following coefficient multiplication as both data and coefficient are non-negative.

Abstract: A weather band receiver, which may be part of an FM receiver, is disclosed. FSK-encoded data units in an alert packet transmission are detected using a quadrature matched filter circuit. At least one FSK-encoded data unit is captured from the alert packet transmission. Soft quantized bits are extracted from the FSK-encoded data units. The soft quantized bits are saved to memory and used to recover an alert message. Soft quantized bits from two or more FSK-encoded data units may be combined before recovering the alert message.

Abstract: A digital data storage and retrieval system. The system has a first memory for storing a plurality of data quantities, and each data quantity, in the plurality of data quantities, consists of a first number of bits. The system also has a second memory for storing a plurality of compressed data quantities, and each compressed data quantity, in the plurality of compressed data quantities, consists of a second number of bits that is less than the first number of bits. The system also has circuitry for reading data quantities from the first memory and circuitry for writing compressed data quantities, corresponding to respective read data quantities, to non-sequential addresses in the second memory. The system also may include circuitry for reading compressed data quantities from the second memory, and circuitry for writing decompressed data quantities, corresponding to respective read compressed data quantities, to non-sequential addresses in the first memory.

Abstract: A digital circuit includes at least one input node, a biasing circuit, and a digital baseband circuit. The input node receives a digital signal including samples at a plurality of sample instances, the samples including a positive sample and a negative sample and represented by first plurality of bits. The biasing circuit generates a biased digital signal by adding a bias value to the digital signal so as to change the positive sample and the negative sample to first sample and second sample respectively and represented by second plurality of bits. The digital baseband circuit is configured to receive and process the biased digital signal such that reduced current consumption is realized based on a number of bit toggles in the second plurality of bits being less than a number of bit toggles in the first plurality of bits.

Abstract: An apparatus and method for reducing interference signals using multiphase clocks. An integrated circuit includes a digital circuit and an analog circuit. The digital circuit includes a derived clock circuit configured to receive a root clock having a frequency D*f, D being a divide factor, to divide the root clock by D, and generate multiphase clocks having N phases. N circuits of the digital circuit are configured to receive a corresponding one of the N phases, with edges of the multiphase clocks being spread over the N phases. The multiphase clocks cause a frequency shift in interference signals generated by reduced periodic peak currents drawn by the N circuits from f to N*f and harmonics thereof. The analog circuit receives an in-band range of signals. A value of N is configured to shift the interference signals outside the in-band range of signals.

Abstract: A digital circuit includes at least one input node, a biasing circuit, and a digital baseband circuit. The input node receives a digital signal including samples at a plurality of sample instances, the samples including a positive sample and a negative sample and represented by first plurality of bits. The biasing circuit generates a biased digital signal by adding a bias value to the digital signal so as to change the positive sample and the negative sample to first sample and second sample respectively and represented by second plurality of bits. The digital baseband circuit is configured to receive and process the biased digital signal such that reduced current consumption is realized based on a number of bit toggles in the second plurality of bits being less than a number of bit toggles in the first plurality of bits.

Abstract: One embodiment of the invention includes a receiver system. The system includes a receiver that generates digital data samples corresponding to an analog signal at a sampling frequency associated with a first frequency reference and a host codec that reads the digital data samples at a read frequency associated with a second frequency reference. The system also includes a first-in first-out (FIFO) buffer that buffers the digital data samples via write commands associated with the receiver and read commands associated with the host codec. The FIFO buffer can have a current pointer state that is based on the relative write and read commands. The system further includes a frequency controller that calculates a frequency offset between the sampling frequency and the read frequency based on a rate of drift of the current pointer state relative to a predetermined calibration threshold and adjusts the sampling frequency based on the frequency offset.

Abstract: An apparatus and method for reducing interference signals using multiphase clocks. An integrated circuit includes a digital circuit and an analog circuit. The digital circuit includes a derived clock circuit configured to receive a root clock having a frequency D*f, D being a divide factor, to divide the root clock by D, and generate multiphase clocks having N phases. N circuits of the digital circuit are configured to receive a corresponding one of the N phases, with edges of the multiphase clocks being spread over the N phases. The multiphase clocks cause a frequency shift in interference signals generated by reduced periodic peak currents drawn by the N circuits from f to N*f and harmonics thereof. The analog circuit receives an in-band range of signals. A value of N is configured to shift the interference signals outside the in-band range of signals.