Abstract: Embodiments of the present disclosure relate to a neural engine of a neural processor circuit having multiple multiply-add circuits and an accumulator circuit coupled to the multiply-add circuits. The multiply-add circuits perform multiply-add operations of a three dimensional convolution on a work unit of input data using a kernel to generate at least a portion of output data in a processing cycle. The accumulator circuit includes multiple batches of accumulators. Each batch of accumulators receives and stores, after the processing cycle, the portion of the output data for each output depth plane of multiple output depth planes. A corresponding batch of accumulators stores, after the processing cycle, the portion of the output data for a subset of the output channels and for each output depth plane.

Abstract: Embodiments relate to a compiler. The compiler decreases data fetch and read associated with storing data in a data buffer of a neural processor circuit to or from a system memory. The data buffer can store an input slice of data for processing by a neural engine(s) of the neural processor circuit, an output slice of data output from the neural engine(s), and/or an intermediate data slice of data.

Abstract: Embodiments relate to a neural processor circuit with scalable architecture for instantiating one or more neural networks. The neural processor circuit includes a data buffer coupled to a memory external to the neural processor circuit, and a plurality of neural engine circuits. To execute tasks that instantiate the neural networks, each neural engine circuit generates output data using input data and kernel coefficients. A neural processor circuit may include multiple neural engine circuits that are selectively activated or deactivated according to configuration data of the tasks. Furthermore, an electronic device may include multiple neural processor circuits that are selectively activated or deactivated to execute the tasks.

Abstract: Disclosed are a novel strain of Bacillus amyloliquefaciens, a method of producing fermented grains using the strain, fermented grains produced using the strain, and a composition for thrombolysis; digestion improvement; prophylaxis, amelioration or treatment of bowel inflammation, serous membrane weakening or intestinal injury; or antioxidation, comprising the fermented grains.

Abstract: Embodiments of the present disclosure relate to a neural engine of a neural processor circuit having multiple multiply-add circuits and an accumulator circuit coupled to the multiply-add circuits. The multiply-add circuits perform multiply-add operations of a three dimensional convolution on a work unit of input data using a kernel to generate at least a portion of output data in a processing cycle. The accumulator circuit includes multiple batches of accumulators. Each batch of accumulators receives and stores, after the processing cycle, the portion of the output data for each output depth plane of multiple output depth planes. A corresponding batch of accumulators stores, after the processing cycle, the portion of the output data for a subset of the output channels and for each output depth plane.

Abstract: Embodiments relate to a neural processor circuit with scalable architecture for instantiating one or more neural networks. The neural processor circuit includes a data buffer coupled to a memory external to the neural processor circuit, and a plurality of neural engine circuits. To execute tasks that instantiate the neural networks, each neural engine circuit generates output data using input data and kernel coefficients. A neural processor circuit may include multiple neural engine circuits that are selectively activated or deactivated according to configuration data of the tasks. Furthermore, an electronic device may include multiple neural processor circuits that are selectively activated or deactivated to execute the tasks.

Abstract: Embodiments relate to a neural processor circuit including a plurality of neural engine circuits, a data buffer, and a kernel fetcher circuit. At least one of the neural engine circuits is configured to receive matrix elements of a matrix as at least the portion of the input data from the data buffer over multiple processing cycles. The at least one neural engine circuit further receives vector elements of a vector from the kernel fetcher circuit, wherein each of the vector elements is extracted as a corresponding kernel to the at least one neural engine circuit in each of the processing cycles. The at least one neural engine circuit performs multiplication between the matrix and the vector as a convolution operation to produce at least one output channel of the output data.

Abstract: Embodiments of the present disclosure relate to a neural engine of a neural processor circuit having multiple multiply-add circuits and an accumulator circuit coupled to the multiply-add circuits. The multiply-add circuits perform multiply-add operations of a three dimensional convolution on a work unit of input data using a kernel to generate at least a portion of output data in a processing cycle. The accumulator circuit includes multiple batches of accumulators. Each batch of accumulators receives and stores, after the processing cycle, the portion of the output data for each output depth plane of multiple output depth planes. A corresponding batch of accumulators stores, after the processing cycle, the portion of the output data for a subset of the output channels and for each output depth plane.

Abstract: Embodiments relate to a compiler. The compiler decreases data fetch and read associated with storing data in a data buffer of a neural processor circuit to or from a system memory. The data buffer can store an input slice of data for processing by a neural engine(s) of the neural processor circuit, an output slice of data output from the neural engine(s), and/or an intermediate data slice of data.

Abstract: Embodiments relate to a neural engine circuit of a neural network processor circuit that performs a convolution operation on input data in a first mode and a parallel sorting operation on input data in a second mode. The neural engine circuit includes a plurality of operation circuits and an accumulator circuit coupled to the plurality of operation circuits. The plurality of operation circuits receives input data. In the first mode, the plurality of operation circuits performs multiply-add operations of a convolution on the input data using a kernel. In the second mode, the plurality of operation circuits performs a portion of a parallel sorting operation on the input data. In the first mode, the accumulator circuit receives and stores first results of the multiply-add operations. In the second mode, the accumulator circuit receives and stores second results of the parallel sorting operation.

Abstract: Embodiments relate to a compiler. The compiler decreases data fetch and read associated with storing data in a data buffer of a neural processor circuit to or from a system memory. The data buffer can store an input slice of data for processing by a neural engine(s) of the neural processor circuit, an output slice of data output from the neural engine(s), and/or an intermediate data slice of data.

Abstract: A method for increasing serum half-life of a protein or peptide and decreasing immunogenicity thereof is disclosed. The method includes site-specifically binding a carrier to a protein or peptide. A protein or peptide produced by the method and the uses thereof are disclosed. The conjugate of the physiologically active protein or peptide can significantly decrease immunogenicity in the human body and thus reduce antibody production rate against the protein or peptide. Therefore, the present conjugate has advantages in that a phenomenon of reduced clinical effects of the physiologically active protein or peptide is low, and it can be effectively used in the development of long-acting formulations having a high safety against the immune response.

Abstract: The present invention relates to a sweetening material composition and a method for preparing the same. Specifically, the present invention relates to a sweetening material composition including transglycosylation steviol glycosides and a method for preparing the same. The sweetening material composition of the present invention includes transglycosylated stevia and saccharides, and the saccharides include 5 to 90 parts by weight of an oligosaccharide having a degree of polymerization (DP) of 3 or more with respect to 100 parts by weight.

Abstract: Embodiments relate to a neural processor circuit that includes a kernel access circuit and multiple neural engine circuits. The kernel access circuit reads compressed kernel data from memory external to the neural processor circuit. Each neural engine circuit receives compressed kernel data from the kernel access circuit. Each neural engine circuit includes a kernel extract circuit and a kernel multiply-add (MAD) circuit. The kernel extract circuit extracts uncompressed kernel data from the compressed kernel data. The kernel MAD circuit receives the uncompressed kernel data from the kernel extract circuit and performs neural network operations on a portion of input data using the uncompressed kernel data.

Abstract: A transparent display device comprises: a first substrate including a display area and first to fourth bezel areas surrounding the display area, wherein the display area includes a plurality of pixel regions each including an emitting portion and a transparent portion; a second substrate facing the first substrate; a transparent dam between the first and second substrates and in the first to fourth bezel areas; a first pad electrode on the first substrate and in the first bezel area; and a first color filter pattern on the second substrate and in the first bezel area.

Abstract: Embodiments relate to a neural processor circuit including neural engines, a buffer, and a kernel access circuit. The neural engines perform convolution operations on input data and kernel data to generate output data. The buffer is between the neural engines and a memory external to the neural processor circuit. The buffer stores input data for sending to the neural engines and output data received from the neural engines. The kernel access circuit receives one or more kernels from the memory external to the neural processor circuit. The neural processor circuit operates in one of multiple modes, at least one of which divides a convolution operation into multiple independent convolution operations for execution by the neural engines.

Abstract: A modified IgG4 Fc fragment useful as a drug carrier is disclosed. When coupled to a drug, the resulting drug-IgG4 Fc conjugate can minimize the effector functions of the IgG4 Fc and the chain exchange with in vivo IgG while maintaining in vivo activity and improving in vivo duration of the drug conjugate.

Abstract: Embodiments relate to a neural processor circuit that includes a kernel access circuit and multiple neural engine circuits. The kernel access circuit reads compressed kernel data from memory external to the neural processor circuit. Each neural engine circuit receives compressed kernel data from the kernel access circuit. Each neural engine circuit includes a kernel extract circuit and a kernel multiply-add (MAD) circuit. The kernel extract circuit extracts uncompressed kernel data from the compressed kernel data. The kernel MAD circuit receives the uncompressed kernel data from the kernel extract circuit and performs neural network operations on a portion of input data using the uncompressed kernel data.

Abstract: Embodiments of the present disclosure relate to a neural engine of a neural processor circuit having multiple multiply-add circuits and an accumulator circuit coupled to the multiply-add circuits. The multiply-add circuits perform multiply-add operations of a three dimensional convolution on a work unit of input data using a kernel to generate at least a portion of output data in a processing cycle. The accumulator circuit includes multiple batches of accumulators. Each batch of accumulators receives and stores, after the processing cycle, the portion of the output data for each output depth plane of multiple output depth planes. A corresponding batch of accumulators stores, after the processing cycle, the portion of the output data for a subset of the output channels and for each output depth plane.

Abstract: The present invention relates to a modified IgG4 Fc fragment useful as a drug carrier. When the modified IgG4 Fc fragment of the present invention is combined with an arbitrary drug, the resulting drug conjugate can minimize the effector functions of the IgG4 Fc and the chain exchange with in vivo IgG while maintaining in vivo activity and improving in vivo duration of the drug conjugate.