Abstract: An image encoding/decoding method and apparatus for performing representative sample-based intra prediction are provided. An image decoding method may comprise deriving an intra prediction mode of a current block, configuring a reference sample of the current block, and performing intra prediction for the current block based on the intra prediction mode and the reference sample, wherein the intra prediction is representative sample-based prediction.

Abstract: An image encoding/decoding method and apparatus for performing intra prediction using a plurality of reference sample lines are provided. An image decoding method may comprise configuring a plurality of reference sample lines, reconstructing an intra prediction mode of a current block, and performing intra prediction for the current block based on the intra prediction mode and the plurality of reference sample lines.

Abstract: Disclosed herein are a video decoding method and apparatus and a video encoding method and apparatus. In video encoding and decoding, multiple partition blocks are generated by splitting a target block. A prediction mode is derived for at least a part of the multiple partition blocks, among the multiple partition blocks, and prediction is performed on the multiple partition blocks based on the derived prediction mode. When prediction is performed on the partition blocks, information related to the target block may be used, and information related to an additional partition block, which is predicted prior to the partition block, may be used.

Abstract: Provided are a stream reprocessing system on chip (SoC) and a method for operating the same is provided. The stream reprocessing system includes a plurality of processors including a central processing unit (CPU); a memory controller configured to receive a stream; and a stream reprocessor configured to perform reprocessing the stream, wherein the stream reprocessor includes: a control unit configured to determine whether to perform the reprocessing on the stream; a reprocessing unit configured to reprocess the stream based on receiving a command to perform the reprocessing on the stream from the control unit; and an output unit configured to transmit the reprocessed stream to a memory.

Abstract: An image processing device for performing a data decompression is provided. The image processing device includes a decoder circuit having a plurality of stages for decompressing compressed image data of a plurality of pixels. The decoder circuit is configured to divide the pixels into a plurality of groups. The first stage performs prediction compensation on the compressed image data of a first pixel of the first group at a first time to generate first prediction data, and performs the prediction compensation on the compressed image data of a second pixel of the first group at a second time using the first prediction data. The second stage performs the prediction compensation on the compressed image data of a first pixel of the second group at the second time using the first prediction data, to generate second prediction data.

Abstract: Provided are a stream reprocessing system on chip (SoC) and a method for operating the same is provided. The stream reprocessing system includes a plurality of processors including a central processing unit (CPU); a memory controller configured to receive a stream; and a stream reprocessor configured to perform reprocessing the stream, wherein the stream reprocessor includes: a control unit configured to determine whether to perform the reprocessing on the stream; a reprocessing unit configured to reprocess the stream based on receiving a command to perform the reprocessing on the stream from the control unit; and an output unit configured to transmit the reprocessed stream to a memory.

Abstract: An image processing device includes a multimedia intellectual property (IP) block which processes image data including a first component and a second component; a memory; and a frame buffer compressor (FBC) which compresses the image data to generate compressed data and stores the compressed data in the memory. The frame buffer compressor includes a logic circuit which controls a compression sequence of the first component and the second component of the image data.

Abstract: The present disclosure provides an image processing device. The image processing device includes a multimedia processor and a frame buffer compressor. For example, the frame buffer compressor performs a first compression on first image data including at least a most significant bit (MSB) of the image data of the pixel. The frame buffer compressor performs a second compression on second image data including at least a least significant bit (LSB) of the image data of the pixel. According to techniques described herein, a compression type of the first compression (e.g., a compression type based on a constant bit rate (CBR) mode, fixed bit coding, quad-tree coding, etc.) is different from a compression type of the second compression (e.g., a compression type based on a variable bit rate (VBR) mode, Golomb-Rice coding, Huffman coding, etc.).

Abstract: An image processing device includes a multimedia intellectual (IP) block which processes image data; a memory; and a frame buffer compressor (FBC) which compresses the image data to generate compressed data and stores the compressed data in the memory. The frame buffer compressor includes a logic circuit which determines a combination of a quantization parameter (QP) table and an entropy table and controls compression of the image data based on the determined combination of the QP table and the entropy table.

Abstract: Provided is an image processing device configured to compress first image data. The image processing device includes an encoding circuit configured to compress the first image data into second image data including prediction data and residual data, compress the second image data into third image data by performing entropy encoding on the second image data, generate a header representing a compression ratio of the third image data, and store the third image data along with the header in a memory device as compressed first image data.

Abstract: An image processing device includes a multimedia IP including a plurality of IP cores, at least one of which processes image data to generate source data, a frame buffer compressor, shared by the plurality of IP cores, compressing the source data to generate compressed data, and a memory coupled to the frame buffer compressor and accessed by the multimedia IP through the frame buffer compressor so that the compressed data is stored in the memory. The frame buffer compressor includes a quantization module which performs quantizing on the source data to generate recon data and a prediction module which executes intra-prediction on the recon data to generate prediction data.

Abstract: Provided is an image processing device configured to compress first image data. The image processing device includes an encoding circuit configured to compress the first image data into second image data including prediction data and residual data, compress the second image data into third image data by performing entropy encoding on the second image data, generate a header representing a compression ratio of the third image data, and store the third image data along with the header in a memory device as compressed first image data.

Abstract: An image processing device for performing a data decompression is provided. The image processing device includes a decoder circuit having a plurality of stages for decompressing compressed image data of a plurality of pixels. The decoder circuit is configured to divide the pixels into a plurality of groups. The first stage performs prediction compensation on the compressed image data of a first pixel of the first group at a first time to generate first prediction data, and performs the prediction compensation on the compressed image data of a second pixel of the first group at a second time using the first prediction data. The second stage performs the prediction compensation on the compressed image data of a first pixel of the second group at the second time using the first prediction data, to generate second prediction data.

Abstract: An image processing device for performing a data decompression is provided. The image processing device includes a decoder circuit having a plurality of stages for decompressing compressed image data of a plurality of pixels. The decoder circuit is configured to divide the pixels into a plurality of groups. The first stage performs prediction compensation on the compressed image data of a first pixel of the first group at a first time to generate first prediction data, and performs the prediction compensation on the compressed image data of a second pixel of the first group at a second time using the first prediction data. The second stage performs the prediction compensation on the compressed image data of a first pixel of the second group at the second time using the first prediction data, to generate second prediction data.

Abstract: A video encoding apparatus may include a partitioning unit which divides a frame included in input video into a plurality of blocks and a rate control module which adjusts a first quantization parameter value of a block corresponding to a region of interest among the plurality of blocks based on a first CBF (current buffer fullness) value of the region of interest, and adjusts a second quantization parameter value of a block corresponding to a non-region of interest among the plurality of blocks based on a second CBF value of the non-region of interest.

Abstract: An image processing device includes a multimedia intellectual property (IP) block which processes image data including a first component and a second component; a memory; and a frame buffer compressor (FBC) which compresses the image data to generate compressed data and stores the compressed data in the memory. The frame buffer compressor includes a logic circuit which controls a compression sequence of the first component and the second component of the image data.

Abstract: An image processing device includes a frame buffer compressor, which is configured to: (i) compress source data into compressed data having CRC bits appended thereto, and (ii) decompress the compressed data into output data and use the CRC bits to check for errors in the output data. A multimedia device is provided, which is configured to generate the source data in response to raw data. A memory device is provided, which is configured to store the compressed data. The frame buffer compressor may include an encoder configured to compress the source data into the compressed data with the CRC bits appended thereto, and a decoder configured to decompress the compressed data into the output data. The encoder may include a prediction module, which is configured to generate prediction data including reference data and residual data, from the source data.

Abstract: A video encoding apparatus may include a memory storing interest region information for each of a plurality of scenarios and a neural processing unit (NPU) extracting interest region information corresponding to a scenario of an input video from the memory or updating the interest region information stored in the memory based on an user input.

Abstract: An image processing device includes a multimedia intellectual property (IP) block which processes image data including a first component and a second component; a memory; and a frame buffer compressor (FBC) which compresses the image data to generate compressed data and stores the compressed data in the memory. The frame buffer compressor includes a logic circuit which controls a compression sequence of the first component and the second component of the image data.

Abstract: A video processing device configured to encode frames divided into a plurality of layers according to a prediction type includes a pre-processing circuit configured to, generate a mode analysis result by analyzing mode information for each of N neighboring frames neighboring a target frame, and determine a target layer bit numbers allocated to each of the plurality of layers based on the mode analysis result, N being an integer equal to or greater than 2; and a first encoder configured to encode the target frame according to the determined target layer bit numbers.