Patents by Inventor Sung Yoon Chung

Sung Yoon Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230033065
    Abstract: Disclosed is a polycrystalline ceramic dielectric comprising: crystal grain bulks made of a barium titanate-based ceramic; and grain boundaries comprising interfaces between the crystal grain bulks, wherein the composition of the grain boundaries is controlled using dopants. By controlling the grain boundary composition using dopants so that the dopants are distributed across a width of 5 nm or less and using a nano-sized, fine-grained barium titanate-based ceramic precursor, the grain boundary structure within the polycrystals may maintain electroneutrality, and their ferroelectricity may be controlled, thereby allowing for smoother polarization reaction.
    Type: Application
    Filed: April 26, 2022
    Publication date: February 2, 2023
    Inventors: Sung-Yoon CHUNG, Ji-Sang AN
  • Publication number: 20220177371
    Abstract: Disclosed are a dielectric ceramic includes a plurality of crystal grain bulks including a ceramic, and a grain boundary between the plurality of crystal grain bulks, wherein a dopant is segregated in the grain boundary.
    Type: Application
    Filed: November 22, 2021
    Publication date: June 9, 2022
    Inventors: Sung-Yoon CHUNG, Ji-Sang AN, Hae Seung LEE
  • Patent number: 11329053
    Abstract: Semiconductor devices and methods of forming the same are provided. The methods may include forming first and second line patterns. The first line pattern has a first side facing the second line pattern, and the second line pattern has a second side facing the first line pattern. The methods may also include forming a first spacer structure on the first side of the first line pattern and a second spacer structure on the second side of the second line pattern. The first and the second spacer structures may define an opening. The methods may further include forming a first conductor in a lower part of the opening, forming an expanded opening by etching upper portions of the first and second spacer structures, and forming a second conductor in the expanded opening. The expanded opening may have a width greater than a width of the lower part of the opening.
    Type: Grant
    Filed: January 12, 2021
    Date of Patent: May 10, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yoon Ho Son, Jae Uk Shin, Yong Sun Ko, Im Soo Park, Sung Yoon Chung
  • Patent number: 11289709
    Abstract: Disclosed is a catalyst having a perovskite structure in the form of ABO3, in which the number of ion moles at the A site has an excess ratio compared to the number of ion moles at the B site. The present invention exhibits an oxygen catalytic activity improved by about 3 times in an oxygen evolution reaction and by about 40% in an oxygen reduction reaction, compared to those of an existing LaNiO3 perovskite catalyst. Further, since the metallic conductivity is not significantly changed compared to the existing LaNiO3 perovskite oxide, there is an advantage in that a carbon support need not be used when the present invention is used as a catalyst in a battery positive electrode.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: March 29, 2022
    Assignee: Korea Advanced Institute of Science and Technology
    Inventors: Sung Yoon Chung, Ju Mi Bak
  • Publication number: 20210134809
    Abstract: Semiconductor devices and methods of forming the same are provided. The methods may include forming first and second line patterns. The first line pattern has a first side facing the second line pattern, and the second line pattern has a second side facing the first line pattern. The methods may also include forming a first spacer structure on the first side of the first line pattern and a second spacer structure on the second side of the second line pattern. The first and the second spacer structures may define an opening. The methods may further include forming a first conductor in a lower part of the opening, forming an expanded opening by etching upper portions of the first and second spacer structures, and forming a second conductor in the expanded opening. The expanded opening may have a width greater than a width of the lower part of the opening.
    Type: Application
    Filed: January 12, 2021
    Publication date: May 6, 2021
    Inventors: Yoon Ho Son, Jae Uk Shin, Yong Sun Ko, Im Soo Park, Sung Yoon Chung
  • Patent number: 10916549
    Abstract: Semiconductor devices and methods of forming the same are provided. The methods may include forming first and second line patterns. The first line pattern has a first side facing the second line pattern, and the second line pattern has a second side facing the first line pattern. The methods may also include forming a first spacer structure on the first side of the first line pattern and a second spacer structure on the second side of the second line pattern. The first and the second spacer structures may define an opening. The methods may further include forming a first conductor in a lower part of the opening, forming an expanded opening by etching upper portions of the first and second spacer structures, and forming a second conductor in the expanded opening. The expanded opening may have a width greater than a width of the lower part of the opening.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: February 9, 2021
    Inventors: Yoon Ho Son, Jae Uk Shin, Yong Sun Ko, Im Soo Park, Sung Yoon Chung
  • Publication number: 20200299197
    Abstract: The present disclosure provides a method for preparing a dielectric which can provide a low-dielectric loss dielectric not variable to frequency, wherein the dielectric shows a narrow variation in dielectric characteristics depending on temperature, undergoes no change in dielectric characteristics depending on frequency and thus has a low dielectric loss. The present disclosure also provides a dielectric prepared by the method.
    Type: Application
    Filed: September 3, 2019
    Publication date: September 24, 2020
    Inventors: Sung-Yoon Chung, Ji-Sang An
  • Patent number: 10577285
    Abstract: Provided is a method for preparing a grain boundary insulation-type dielectric. The method includes the steps of obtaining a titanic acid compound and a ferroelectric having a value less than a melting point of the titanic acid compound; obtaining a mixture by adding the ferroelectric material to the titanic acid compound; and sintering the mixture at a temperature equal to or more than a melting point of the ferroelectric material.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: March 3, 2020
    Assignee: Korea Advanced Institute of Science and Technology
    Inventors: Sung Yoon Chung, Hye In Yoon, Gi Young Jo
  • Publication number: 20200013782
    Abstract: Semiconductor devices and methods of forming the same are provided. The methods may include forming first and second line patterns. The first line pattern has a first side facing the second line pattern, and the second line pattern has a second side facing the first line pattern. The methods may also include forming a first spacer structure on the first side of the first line pattern and a second spacer structure on the second side of the second line pattern. The first and the second spacer structures may define an opening. The methods may further include forming a first conductor in a lower part of the opening, forming an expanded opening by etching upper portions of the first and second spacer structures, and forming a second conductor in the expanded opening. The expanded opening may have a width greater than a width of the lower part of the opening.
    Type: Application
    Filed: September 16, 2019
    Publication date: January 9, 2020
    Inventors: Yoon Ho SON, Jae Uk SHIN, Yong Sun KO, Im Soo PARK, Sung Yoon CHUNG
  • Patent number: 10418366
    Abstract: Semiconductor devices and methods of forming the same are provided. The methods may include forming first and second line patterns. The first line pattern has a first side facing the second line pattern, and the second line pattern has a second side facing the first line pattern. The methods may also include forming a first spacer structure on the first side of the first line pattern and a second spacer structure on the second side of the second line pattern. The first and the second spacer structures may define an opening. The methods may further include forming a first conductor in a lower part of the opening, forming an expanded opening by etching upper portions of the first and second spacer structures, and forming a second conductor in the expanded opening. The expanded opening may have a width greater than a width of the lower part of the opening.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: September 17, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yoon Ho Son, Jae Uk Shin, Yong Sun Ko, Im Soo Park, Sung Yoon Chung
  • Publication number: 20180342521
    Abstract: Semiconductor devices and methods of forming the same are provided. The methods may include forming first and second line patterns. The first line pattern has a first side facing the second line pattern, and the second line pattern has a second side facing the first line pattern. The methods may also include forming a first spacer structure on the first side of the first line pattern and a second spacer structure on the second side of the second line pattern. The first and the second spacer structures may define an opening. The methods may further include forming a first conductor in a lower part of the opening, forming an expanded opening by etching upper portions of the first and second spacer structures, and forming a second conductor in the expanded opening. The expanded opening may have a width greater than a width of the lower part of the opening.
    Type: Application
    Filed: January 4, 2018
    Publication date: November 29, 2018
    Inventors: Yoon Ho Son, Jae Uk Shin, Yong Sun Ko, Im Soo Park, Sung Yoon Chung
  • Publication number: 20180331370
    Abstract: Disclosed is a catalyst having a perovskite structure in the form of ABO3, in which the number of ion moles at the A site has an excess ratio compared to the number of ion moles at the B site. The present invention exhibits an oxygen catalytic activity improved by about 3 times in an oxygen evolution reaction and by about 40% in an oxygen reduction reaction, compared to those of an existing LaNiO3 perovskite catalyst. Further, since the metallic conductivity is not significantly changed compared to the existing LaNiO3 perovskite oxide, there is an advantage in that a carbon support need not be used when the present invention is used as a catalyst in a battery positive electrode.
    Type: Application
    Filed: May 7, 2018
    Publication date: November 15, 2018
    Inventors: Sung Yoon Chung, Ju Mi Bak
  • Publication number: 20180327317
    Abstract: Provided is a method for preparing a grain boundary insulation-type dielectric. The method includes the steps of obtaining a titanic acid compound and a ferroelectric having a value less than a melting point of the titanic acid compound; obtaining a mixture by adding the ferroelectric material to the titanic acid compound; and sintering the mixture at a temperature equal to or more than a melting point of the ferroelectric material.
    Type: Application
    Filed: May 7, 2018
    Publication date: November 15, 2018
    Inventors: Sung Yoon Chung, Hye In Yoon, Gi Young Jo
  • Publication number: 20180251381
    Abstract: Provided is a polycrystalline oxide having a chemical formula such as the following A1?xB1?yMyO3 and having an improved grain boundary proton conductivity as an oxide having a perovskite structure. Through the present invention, the conductivity and chemical stability of proton conducting oxide may be improved.
    Type: Application
    Filed: October 5, 2017
    Publication date: September 6, 2018
    Inventors: Sung-Yoon Chung, Hyesung Kim
  • Patent number: 9318697
    Abstract: In a method of detecting an etch by-product, the method including forming a magnetic layer including palladium (Pd) on a substrate; etching the magnetic layer to form a magnetic layer pattern; depositing a mixture including an alkyl bromide compound on a surface of the magnetic layer pattern; and measuring a current difference between the substrate and the mixture to detect an etch by-product on the surface of the magnetic layer pattern.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: April 19, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-Hye Bae, Won-Jun Lee, Sung-Yoon Chung, Taek-Dong Chung
  • Publication number: 20150179927
    Abstract: In a method of detecting an etch by-product, the method including forming a magnetic layer including palladium (Pd) on a substrate; etching the magnetic layer to form a magnetic layer pattern; depositing a mixture including an alkyl bromide compound on a surface of the magnetic layer pattern; and measuring a current difference between the substrate and the mixture to detect an etch by-product on the surface of the magnetic layer pattern.
    Type: Application
    Filed: August 1, 2014
    Publication date: June 25, 2015
    Inventors: Jin-Hye BAE, Won-Jun LEE, Sung-Yoon CHUNG, Taek-Dong CHUNG
  • Patent number: 8852807
    Abstract: A compound comprising a composition Ax(M?1?aM?a)y(XD4)z, Ax(M?1?aM?a)y(DXD4)z, or Ax(M?1?aM?a)y(X2D7)z, (A1?aM?a)xM?y(XD4)z, (A1?aM?a)xM?y(DXD4)z, or (A1?aM?a)xM?y(X2D7)z. In the compound, A is at least one of an alkali metal and hydrogen, M? is a first-row transition metal, X is at least one of phosphorus, sulfur, arsenic, molybdenum, and tungsten, M? any of a Group IIA, IIIA, IVA, VA, VIA, VIIA, VIIIA, IB, IIB, IIIB, IVB, VB, and VIB metal, D is at least one of oxygen, nitrogen, carbon, or a halogen, 0.0001<a?0.1, and x, y, and z are greater than zero. The compound can be used in an electrochemical device including electrodes and storage batteries.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: October 7, 2014
    Assignee: Massachusetts Institute of Technology
    Inventors: Yet-Ming Chiang, Sung-Yoon Chung, Jason T. Bloking, Anna M. Andersson
  • Patent number: 8480987
    Abstract: Provided are lithium transition metal phosphates where the cation anti-site defects between lithium and transition metals in a lithium transition metal phosphate with a cation well-ordered olivine structure are arranged only in a 1D crystal direction, and a method of preparing the same. The method comprises adding any one selected from the group consisting of an alkali element and an element that has a valence of 5+ or any combination thereof to a solid salt comprising lithium, transition metals, and phosphorus as a starting material to produce a first intermediate material; subjecting the first intermediate to a first heat treatment at a temperature of approximately 250° C. to approximately 400° C. to produce a second amorphous material; and cooling the second intermediate material to room temperature, followed by a second heat treatment at a temperature of approximately 400° C. to approximately 800° C.
    Type: Grant
    Filed: December 9, 2009
    Date of Patent: July 9, 2013
    Inventor: Sung Yoon Chung
  • Patent number: 8465717
    Abstract: A process for preparing a nanoparticle powder of a lithium transition metal phosphate includes mixing lithium, a transition metal and a phosphorus-containing salt as starting materials, adding an additive to the starting materials in an amount of greater than 0 at % and less than 10 at % to obtain a mixed raw material powder, subjecting the mixed powder to a first heat treatment at a temperature of 250° C. to 400° C. under a gas atmosphere for 2 to 10 hours; and subjecting the first heat-treated product to a second heat treatment at a temperature of 400° C. to 700° C. for 2 to 24 hours to uniformly form crystalline nuclei so as to induce growth of nanocrystalline particles. The additive may be any one element selected from the group consisting of sodium (Na), potassium (K), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), gadolinium (Gd) and erbium (Er).
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: June 18, 2013
    Inventor: Sung Yoon Chung
  • Publication number: 20120214071
    Abstract: A compound comprising a composition Ax(M?1?aM?a)y(XD4)z, Ax(M?1?aM?a)y(DXD4)z, or Ax(M?1?aM?a)y(X2D7)z, (A1?aM?a)xM?y(XD4)z, (A1?aM?a)xM?y(DXD4)z, or (A1?aM?a)xM?y(X2D7)z. In the compound, A is at least one of an alkali metal and hydrogen, M? is a first-row transition metal, X is at least one of phosphorus, sulfur, arsenic, molybdenum, and tungsten, M? any of a Group IIA, IIIA, IVA, VA, VIA, VIIA, VIIIA, IB, IIB, IIIB, IVB, VB, and VIB metal, D is at least one of oxygen, nitrogen, carbon, or a halogen, 0.0001<a?0.1, and x, y, and z are greater than zero. The compound can be used in an electrochemical device including electrodes and storage batteries.
    Type: Application
    Filed: February 24, 2012
    Publication date: August 23, 2012
    Applicant: Massachusetts Institute of Technology
    Inventors: Yet-Ming Chiang, Sung-Yoon Chung, Jason T. Bloking, Anna M. Andersson