Abstract: The present invention relates to a cooling and heating cabinet device of a rear seat side for a vehicle using a thermoelectric module that is mounted between rear seats of a vehicle, having cooling and heating functions and further having an arm-resting function irrespective of its activation as the cooling and heating device, and that makes the exhaust fan activated by the control of the controller of the air conditioning system, thereby achieving the air-refreshing function as well as the cooling or heating mode function of the cooling and heating cabinet.

Abstract: The present invention relates to an air conditioner for a vehicle that is capable of easily and simply assembling a thermistor-holding device insertedly with a coupling hole formed at one side surface of a lower case of an air conditioning case, while inserting first and second protrusions formed through upper and lower molds around the coupling hole thereto, such that the total number of parts and the working period are all reduced to improve the productivity of the product and the repairing or exchanging work of the thermistor is carried out easily.

Abstract: The present invention relates to an air conditioner for vehicle including a front seat air conditioning unit and a rear seat air conditioning unit.

Abstract: A method for reducing the number of transitions generated by an LFSR is introduced. The transition monitoring window monitors the number of transitions occurring as random patterns generated from an LFSR are applied to a scan chain, and, if the number of transitions exceeds a threshold value (“k-value”), all further transitions are suppressed. The transition monitoring window monitors the patterns entering the LFSR, incrementing a counter if a transition is detected. If a transition is detected just before the exit of a lowest stage of the LFSR the counter is decremented. The signal from the counter is compared with the k-value at every clock tick, and if the count is greater than the k-value, the vector most recently applied to the scan chain is re-applied to the scan chain; if it is less than the k-value, the output from the LFSR is applied to the scan chain.

Abstract: The present invention relates to an air conditioner for a vehicle that is capable of easily and simply assembling a thermistor-holding device insertedly with a coupling hole formed at one side surface of a lower case of an air conditioning case, while inserting first and second protrusions formed through upper and lower molds around the coupling hole thereto, such that the total number of parts and the working period are all reduced to improve the productivity of the product and the repairing or exchanging work of the thermistor is carried out easily.

Abstract: The present invention relates to a dual zone type air conditioner for vehicles, which can freely adjust the air volume supplied to the right and left sides of the inside of the vehicle by mounting a film door between an evaporator and a temp door, realize a perfect independent control by controlling temp doors in such a manner as to allow the temp door mounted at a larger air volume side to be opened smaller than the temp door mounted at a smaller air volume side according to a temperature difference between the right and left sides, minimize eccentricity in cooling effect of the evaporator by minimizing the eccentricity of the air passing through the evaporator, and minimize a load of a blower under a condition where the air volume of the driver's seat or the front passenger's seat is maximized.

Abstract: A method for reducing the number of transitions generated by an LFSR is introduced. The transition monitoring window monitors the number of transitions occurring as random patterns generated from an LFSR are applied to a scan chain, and, if the number of transitions exceeds a threshold value (“k-value”), all further transitions are suppressed. The transition monitoring window monitors the patterns entering the LFSR, incrementing a counter if a transition is detected. If a transition is detected just before the exit of a lowest stage of the LFSR the counter is decremented. The signal from the counter is compared with the k-value at every clock tick, and if the count is greater than the k-value, the vector most recently applied to the scan chain is re-applied to the scan chain; if it is less than the k-value, the output from the LFSR is applied to the scan chain.

Abstract: A method of reducing hardware overhead upon the generation of a test pattern in a built-in self test is introduced, in which two pieces of hardware perform a lot of functions even prior to generation of deterministic patterns, thereby reducing the amount of hardware required for conventional pseudo-random pattern generation while not increasing test time appreciably. This method is characterized in that an LFSR is constructed such that it shifts only one bit among N?1 bits taken from the N bits of an N bit-pattern counter and bit counter to a scan chain.

Abstract: The present invention relates to an air conditioner for a vehicle including a front seat air conditioning unit and a rear seat air conditioning unit.

Abstract: The present invention relates to an air conditioner for vehicle including a front seat air conditioning unit and a rear seat air conditioning unit.

Abstract: The present invention relates to an air conditioner for a vehicle including a front seat air conditioning unit and a rear seat air conditioning unit.

Abstract: A test vector system (157) and method for generating and verifying test vectors for testing integrated circuit speed paths involves accessing a circuit model (160), a list of circuit paths (162) and a test vector verifier (165). A single circuit path, referred to as a selected path, is selected from the paths (162). Once logical constraints are set, hazard-free logical values and logical values for both the second test clock cycle and the first test clock cycle are justified. Test vectors are generated in response to the justified values and the test vectors are used as input to the test vector verifier. The test verifier produces patterns that provide robust delay path fault tests for the given path. The test patterns are serially shifted and double-clocked in an integrated circuit or electrical circuit manufactured in accordance with circuit model (160) to determine time delay path faults.

Abstract: A test vector generator system (157) and method for generating test vectors for testing integrated circuit speed paths involves accessing both a circuit model (160) and a list of circuit paths (162). A single circuit path, referred to as a selected path, is selected from the paths (162), and a set of logic value constraints are set for logic devices in the selected circuit path. These logical constraints are set to ensure that a proper input-to-output transition, which is used to identify speed path faults, results in response to only two clock cycles. Once logical constraints are set, hazard-free logical values and logical values for both the second test clock cycle and the first test clock cycle are justified. Test vectors are generated in response to the justified values and the test vectors are serially shifted and double-clocked in an integrated circuit or electrical circuit manufactured in accordance with circuit model (160) to determine time delay path faults.

Abstract: A test vector generator system (157) and method for generating test vectors for testing integrated circuit speed paths involves accessing both a circuit model (160) and a list of circuit paths (162). A single circuit path, referred to as a selected path, is selected from the paths (162). A set of logic value constraints is set for custom logic blocks, through the use of Boolean differences, and a set of logic value constraints is set for standard logic devices in the selected circuit path. These logical constraints are set to ensure that a proper input-to-output transition, which is used to identify speed path faults, results in response to only two clock cycles. Once logical constraints are set, hazard-free logical values and logical values for both the second test clock cycle and the first test clock cycle are justified.