Abstract: A semiconductor device includes a gate electrode disposed on a fin, a gate spacer disposed on the fin and a sidewall of the gate electrode, a source/drain electrode disposed on the fin, and an air pocket structure interposed between the gate spacer and the source/drain electrode. The air pocket structure includes an air gap, a first sidewall, a top sealing, a second sidewall and a bottom sealing. The air gap is enclosed by the first sidewall, the top sealing, the second sidewall and the bottom sealing arranged in a clockwise sequence. The top sealing and the bottom sealing include the same material of an energy removable material.

Abstract: A semiconductor device includes a gate electrode disposed on a fin, a gate spacer disposed on the fin and a sidewall of the gate electrode, a source/drain electrode disposed on the fin, and an air pocket structure interposed between the gate spacer and the source/drain electrode. The air pocket structure includes an air gap, a first sidewall, a top sealing, a second sidewall and a bottom sealing. The air gap is enclosed by the first sidewall, the top sealing, the second sidewall and the bottom sealing arranged in a clockwise sequence. The top sealing and the bottom sealing include the same material of an energy removable material.

Abstract: The present disclosure relates to methods for forming IC structures having recessed gate spacers and related IC structures. A method may include: forming a first and second dummy gate over a fin, each dummy gate having gate spacers disposed on sidewalls thereof such that an opening is disposed between a first gate spacer and a second gate spacer, the opening exposing a source/drain region; recessing the first and second gate spacers; forming an etch stop layer within the opening such that the etch stop layer extends vertically along the recessed first and second gate spacers; forming a dielectric fill over the etch stop layer to substantially fill the opening; replacing the first and second dummy gates with first and second RMG structures; recessing the first and second RMG structures; and forming a gate cap layer over the first and second RMG structures.

Abstract: Structures for a field-effect transistor and methods for forming a structure for a field-effect transistor. A gate cavity is formed in a dielectric layer that includes a bottom surface and a plurality sidewalls that extend to the bottom surface. A gate dielectric layer is formed at the sidewalls and the bottom surface of the gate cavity. A work function metal layer is deposited on the gate dielectric layer at the sidewalls and the bottom surface of the gate cavity. A fill metal layer is deposited inside the gate cavity after the work function metal layer is deposited. The fill metal layer is formed in direct contact with the work function metal layer.

Abstract: Structures for a field-effect transistor and methods for forming a field-effect transistor. The structure includes a gate structure having a sidewall and a sidewall spacer arranged adjacent to the sidewall of the gate structure. The sidewall spacer includes an energy removal film material and one or more air gaps in the energy removal film material.

Abstract: A process for forming a conductive structure includes the formation of a self-aligned silicide cap over a cobalt-based contact. The silicide cap is formed in situ by the deposition of a thin silicon layer over exposed portions of a cobalt contact, followed by heat treatment to react the deposited silicon with the cobalt and form cobalt silicide, which is an effective barrier to cobalt migration and oxidation.

Abstract: Programmable via devices and fabrication methods thereof are presented. The programmable via devices include, for instance, a first metal layer and a second metal layer electrically connected by a via link. The via link includes a semiconductor portion and a metal portion, where the via link facilitates programming of the programmable via device by applying a programming current through the via link to migrate materials between the semiconductor portion and the metal portion to facilitate a change of an electrical resistance of the via link. In one embodiment, the programming current facilitates formation of at least one gap region within the via link, the at least one gap region facilitating the change of the electrical resistance of the via link.

Abstract: A process for forming a conductive structure includes the formation of a self-aligned silicide cap over a cobalt-based contact. The silicide cap is formed in situ by the deposition of a thin silicon layer over exposed portions of a cobalt contact, followed by heat treatment to react the deposited silicon with the cobalt and form cobalt silicide, which is an effective barrier to cobalt migration and oxidation.

Abstract: Structures that include cobalt metallization and methods of forming such structures. A feature is located inside an opening in a dielectric layer and a cap layer located on a top surface of the feature. The feature is composed of cobalt, and the cap layer is composed of ruthenium or a cobalt-containing alloy.

Abstract: A process for forming a conductive structure includes the formation of a self-aligned silicide cap over a cobalt-based contact. The silicide cap is formed in situ by the deposition of a thin silicon layer over exposed portions of a cobalt contact, followed by heat treatment to react the deposited silicon with the cobalt and form cobalt silicide, which is an effective barrier to cobalt migration and oxidation.

Abstract: Programmable via devices and fabrication methods thereof are presented. The programmable via devices include, for instance, a first metal layer and a second metal layer electrically connected by a via link. The via link includes a semiconductor portion and a metal portion, where the via link facilitates programming of the programmable via device by applying a programming current through the via link to migrate materials between the semiconductor portion and the metal portion to facilitate a change of an electrical resistance of the via link. In one embodiment, the programming current facilitates formation of at least one gap region within the via link, the at least one gap region facilitating the change of the electrical resistance of the via link.

Abstract: Interconnect structures and methods of forming such interconnect structures. A spacer is formed inside an opening in a dielectric layer. After the spacer is formed, a conductive plug is formed inside the opening in the dielectric layer. After the conductive plug is formed, the spacer is removed to define an air gap located inside the opening in the dielectric layer. The air gap is located between the conductive plug and the opening in the dielectric layer.

Abstract: One method disclosed herein includes performing a plurality of conformal deposition processes to form first, second and third layers of material within a contact opening, wherein the first layer comprises a contact insulating material, the second layer comprises a metal-containing material and the third layer comprises a conductive cap material, wherein the third layer is positioned above the second layer. The method further includes forming a contact ion implant region that is positioned at least partially in at least one of the first, second or third layers of material, forming a conductive material above the third layer and removing portions of the layers of material positioned outside of the contact opening.

Abstract: Programmable via devices and fabrication methods thereof are presented. The programmable via devices include, for instance, a first metal layer and a second metal layer electrically connected by a via link. The via link includes a semiconductor portion and a metal portion, where the via link facilitates programming of the programmable via device by applying a programming current through the via link to migrate materials between the semiconductor portion and the metal portion to facilitate a change of an electrical resistance of the via link. In one embodiment, the programming current facilitates formation of at least one gap region within the via link, the at least one gap region facilitating the change of the electrical resistance of the via link.

Abstract: One method disclosed herein includes performing a plurality of conformal deposition processes to form first, second and third layers of material within a contact opening, wherein the first layer comprises a contact insulating material, the second layer comprises a metal-containing material and the third layer comprises a conductive cap material, wherein the third layer is positioned above the second layer. The method further includes forming a contact ion implant region that is positioned at least partially in at least one of the first, second or third layers of material, forming a conductive material above the third layer and removing portions of the layers of material positioned outside of the contact opening.

Abstract: A semiconductor structure includes a dielectric layer, a silicidable metal layer and an undoped filler material layer are used to create an anti-efuse device. The anti-efuse device may be situated in a dielectric layer of an interconnect structure for a semiconductor device or may be planar. Where part of an interconnect structure, the anti-efuse device may be realized by causing a current to flow therethrough while applying local heating. Where planar, the filler material may be situated between extensions of metal pads and metal atoms caused to move from the extensions to the filler material layer using a current flow and local heating.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one embodiment, a method for fabricating integrated circuits includes forming a gate dielectric overlying a substrate, and forming a base work function layer that includes tungsten overlying the gate dielectric. The base work function layer overlies the gate dielectric in a first and second region, where the first region is one of a pFET region or an nFET region and the second region is the other of the pFET region or the nFET region. A mask is formed over the first region, and then the second region is exposed. A work function value of the base work function layer in the second region is altered to produce a modified work function layer. The mask is removed from the over the first region, and a gate electrode is formed overlying the base and modified work function layers.

Abstract: Programmable devices and fabrication methods thereof are presented. The programmable devices include, for instance, a first electrode and a second electrode electrically connected by a link portion. The link portion includes one material of a metal material or a semiconductor material and the first and second electrodes includes the other material of the metal material or the semiconductor material. For example, the link portion facilitates programming the programmable device by applying a programming current between the first electrode and the second electrode to facilitate migration of the one material of the link portion towards at least one of the first or second electrodes. In one embodiment, the programming current is configured to heat the link portion to facilitate the migration of the one material of the link portion towards the at least one of the first or second electrodes.

Abstract: A semiconductor structure includes a dielectric layer, a silicidable metal layer and an undoped filler material layer are used to create an anti-efuse device. The anti-efuse device may be situated in a dielectric layer of an interconnect structure for a semiconductor device or may be planar. Where part of an interconnect structure, the anti-efuse device may be realized by causing a current to flow therethrough while applying local heating. Where planar, the filler material may be situated between extensions of metal pads and metal atoms caused to move from the extensions to the filler material layer using a current flow and local heating.

Abstract: Methods of facilitating fabrication of circuit structures are provided which include, for instance: providing a structure with a film layer; modifying an etch property of the film layer by implanting at least one species of element or molecule into the upper portion of the film layer, the etch property of the film layer remaining unmodified beneath the upper portion; and subjecting the structure and film layer with the modified etch property to an etching process, the modified etch property of the film layer facilitating the etching process. Modifying the etch property of the upper portion of the film layer may include making the upper portion of the film layer preferentially susceptible or preferentially resistant to the etching process depending on the circuit fabrication approach being facilitated.