Patents by Inventor Suraj K. Patil
Suraj K. Patil has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9613855Abstract: A method that includes, among other things, forming first and second contact openings in a layer of insulating material that respectively expose a portion of first and second source/drain (S/D) regions of first and second transistors that are of the opposite type, forming first, second and third layers of material within each of the first and second contact openings, and forming an implant masking layer that masks the first contact opening while leaving the second contact opening exposed for further processing. The method also includes forming a contact ion implant region that is positioned at least partially in at least one of the first, second or third layers of material, removing the implant masking layer and forming a conductive material in both the first and second contact openings so as to define first and second MIS contact structures positioned in the first and second contact openings.Type: GrantFiled: April 5, 2016Date of Patent: April 4, 2017Assignee: GLOBALFOUNDRIES Inc.Inventors: Suraj K. Patil, Zhiguo Sun, Keith Tabakman
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Publication number: 20170092373Abstract: Programmable devices and fabrication methods thereof are presented. The programmable devices include, for instance, a first electrode and a second electrode electrically connected by a link portion. The link portion includes one material of a metal material or a semiconductor material and the first and second electrodes includes the other material of the metal material or the semiconductor material. For example, the link portion facilitates programming the programmable device by applying a programming current between the first electrode and the second electrode to facilitate migration of the one material of the link portion towards at least one of the first or second electrodes. In one embodiment, the programming current is configured to heat the link portion to facilitate the migration of the one material of the link portion towards the at least one of the first or second electrodes.Type: ApplicationFiled: September 28, 2015Publication date: March 30, 2017Applicant: GLOBALFOUNDRIES Inc.Inventors: Suraj K. PATIL, Min-hwa CHI, Ajey P. JACOB
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Publication number: 20170092583Abstract: Programmable via devices and fabrication methods thereof are presented. The programmable via devices include, for instance, a first metal layer and a second metal layer electrically connected by a via link. The via link includes a semiconductor portion and a metal portion, where the via link facilitates programming of the programmable via device by applying a programming current through the via link to migrate materials between the semiconductor portion and the metal portion to facilitate a change of an electrical resistance of the via link. In one embodiment, the programming current facilitates formation of at least one gap region within the via link, the at least one gap region facilitating the change of the electrical resistance of the via link.Type: ApplicationFiled: September 28, 2015Publication date: March 30, 2017Applicant: GLOBALFOUNDRIES Inc.Inventors: Ajey P. JACOB, Suraj K. PATIL, Min-hwa CHI
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Publication number: 20170062442Abstract: Methods and structures for programmable device fabrication are provided. The methods for fabricating a programmable device include, for example forming at least one via opening in a layer of the programmable device and providing a catalyzing material over a lower surface of the at least one via opening; forming a plurality of nanowires or nanotubes in the at least one via opening using the catalyzing material as a catalyst for the forming of the plurality of nanowires or nanotubes; and providing a dielectric material in the at least one via opening so that the dielectric material surrounds the plurality of nanowires or nanotubes. The programmable device may, in subsequent or separate programming steps, have programming of the programmable device made permanent via thermal oxidation of the dielectric material and the plurality of nanowires or nanotubes, leaving a non-conducting material behind in the at least one via opening.Type: ApplicationFiled: September 1, 2015Publication date: March 2, 2017Applicant: GLOBALFOUNDRIES INC.Inventors: Suraj K. PATIL, Ajey P. JACOB, Min-hwa CHI
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Patent number: 9570572Abstract: There is set forth herein a method of fabricating a contact interface formation. A layer of Ti metal can be deposited on a substrate and a layer of Ni metal can be deposited over the layer of Ti metal. An annealing process can be performed to form a contact interface formation having Ti in reacted form and Ni in reacted form.Type: GrantFiled: October 24, 2014Date of Patent: February 14, 2017Assignee: GLOBALFOUNDRIES Inc.Inventors: Suraj K. Patil, Min-hwa Chi
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Patent number: 9564447Abstract: Methods and structures for programmable device fabrication are provided. The methods for fabricating a programmable device include, for example forming at least one via opening in a layer of the programmable device and providing a catalyzing material over a lower surface of the at least one via opening; forming a plurality of nanowires or nanotubes in the at least one via opening using the catalyzing material as a catalyst for the forming of the plurality of nanowires or nanotubes; and providing a dielectric material in the at least one via opening so that the dielectric material surrounds the plurality of nanowires or nanotubes. The programmable device may, in subsequent or separate programming steps, have programming of the programmable device made permanent via thermal oxidation of the dielectric material and the plurality of nanowires or nanotubes, leaving a non-conducting material behind in the at least one via opening.Type: GrantFiled: September 1, 2015Date of Patent: February 7, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Suraj K. Patil, Ajey P. Jacob, Min-hwa Chi
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Publication number: 20160351675Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes defining a pFET region and an nFET region of a semiconductor substrate. The method deposits a first work function material including tungsten and nitride over the pFET region and the nFET region of the semiconductor substrate. The method includes selectively modifying the first work function material in a selected region. Further, the method includes depositing a metal fill over the first work function material in the pFET region and the nFET region of the semiconductor substrate.Type: ApplicationFiled: May 26, 2015Publication date: December 1, 2016Inventors: Suraj K. Patil, Mitsuhiro Togo
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Patent number: 9502301Abstract: Methods are provided for fabricating multi-layer semiconductor structures. The methods include, for example: providing a first layer and a second layer over a substrate, the first layer including a first metal and the second layer including a second metal, where the second layer is disposed over the first layer and the first metal and second metal are different metals; and annealing the first layer, the second layer, and the substrate to react at least a portion of the first metal of the first layer to form a first reacted layer and at least a portion of the second metal of the second layer to form a second reacted layer, where at least one of the first reacted layer or the second reacted layer includes at least one of a first metal silicide of the first metal or a second metal silicide of the second metal.Type: GrantFiled: June 4, 2015Date of Patent: November 22, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Suraj K. Patil, Min-hwa Chi
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Patent number: 9396995Abstract: A method of forming a metalized contact in MOL is provided. Embodiments include forming a TT through an ILD down to a S/D region; forming a SiOC, SiCN, or SiON layer on side surfaces of the TT; performing a GCIB vertical etching at a 0° angle; implanting Si into the TT by an angled PAI; removing a portion of the TT by Ar sputtering and a remote plasma assisted dry etch process; forming NiSi on the S/D region at the bottom of the TT; and filling the TT with contact metal over the NiSi.Type: GrantFiled: February 27, 2015Date of Patent: July 19, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Suraj K. Patil, Min-hwa Chi, Garo Derderian, Wen-Pin Peng
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Publication number: 20160190014Abstract: Methods are provided for fabricating multi-layer semiconductor structures. The methods include, for example: providing a first layer and a second layer over a substrate, the first layer including a first metal and the second layer including a second metal, where the second layer is disposed over the first layer and the first metal and second metal are different metals; and annealing the first layer, the second layer, and the substrate to react at least a portion of the first metal of the first layer to form a first reacted layer and at least a portion of the second metal of the second layer to form a second reacted layer, where at least one of the first reacted layer or the second reacted layer includes at least one of a first metal silicide of the first metal or a second metal silicide of the second metal.Type: ApplicationFiled: June 4, 2015Publication date: June 30, 2016Applicant: GLOBALFOUNDRIES INC.Inventors: Suraj K. PATIL, Min-hwa CHI
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Publication number: 20160118468Abstract: There is set forth herein a method of fabricating a contact interface formation. A layer of Ti metal can be deposited on a substrate and a layer of Ni metal can be deposited over the layer of Ti metal. An annealing process can be performed to form a contact interface formation having Ti in reacted form and Ni in reacted form.Type: ApplicationFiled: October 24, 2014Publication date: April 28, 2016Applicant: GLOBALFOUNDRIES Inc.Inventors: Suraj K. PATIL, Min-hwa CHI
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Patent number: 9195132Abstract: A lithography mask structure is provided, including: a substrate; at least one reflective layer over the substrate; and an absorber film stack over the at least one reflective layer, the absorber film stack including a plurality of first film layers of a first material and at least one second film layer of a second material. The second material is different from the first material, and the second film layer(s) is interleaved with the plurality of first film layers. In one embodiment, the total thickness of the absorber film stack is less than 50 nm. In another embodiment, the reflectivity of the absorber film stack is less than 2% for a pre-defined wavelength of EUV light. In a further embodiment, the second film layer(s) prevents the average crystallite size of the first film layers from exceeding the thickness of the first film layers.Type: GrantFiled: January 30, 2014Date of Patent: November 24, 2015Assignee: GLOBALFOUNDRIES INC.Inventors: Suraj K. Patil, SherJang Singh, Uzodinma Okoroanyanwu, Obert R. Wood, Pawitter J. S. Mangat
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Publication number: 20150212402Abstract: A lithography mask structure is provided, including: a substrate; at least one reflective layer over the substrate; and an absorber film stack over the at least one reflective layer, the absorber film stack including a plurality of first film layers of a first material and at least one second film layer of a second material. The second material is different from the first material, and the second film layer(s) is interleaved with the plurality of first film layers. In one embodiment, the total thickness of the absorber film stack is less than 50 nm. In another embodiment, the reflectivity of the absorber film stack is less than 2% for a pre-defined wavelength of EUV light. In a further embodiment, the second film layer(s) prevents the average crystallite size of the first film layers from exceeding the thickness of the first film layers.Type: ApplicationFiled: January 30, 2014Publication date: July 30, 2015Applicant: GLOBALFOUNDRIES INC.Inventors: Suraj K. PATIL, SherJang SINGH, Uzodinma OKOROANYANWU, Obert R. WOOD, Pawitter J.S. Mangat
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Publication number: 20150104948Abstract: Methods of facilitating fabrication of circuit structures are provided which include, for instance: providing a structure with a film layer; modifying an etch property of the film layer by implanting at least one species of element or molecule into the upper portion of the film layer, the etch property of the film layer remaining unmodified beneath the upper portion; and subjecting the structure and film layer with the modified etch property to an etching process, the modified etch property of the film layer facilitating the etching process. Modifying the etch property of the upper portion of the film layer may include making the upper portion of the film layer preferentially susceptible or preferentially resistant to the etching process depending on the circuit fabrication approach being facilitated.Type: ApplicationFiled: October 10, 2013Publication date: April 16, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Suraj K. PATIL, Huy CAO, Hui ZHAN, Huang LIU
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Patent number: 9006016Abstract: The present invention provides a method and apparatus for fabricating piezoresistive polysilicon on a substrate by low-temperature metal induced crystallization by: (1) providing the substrate having a passivation layer; (2) performing, at or near room temperature in a chamber without breaking a vacuum or near-vacuum within the chamber, the steps of: (a) creating a metal layer on the passivation layer, and (b) creating an amorphous silicon layer on the metal layer, wherein the metal layer and the amorphous silicon layer have approximately the same thickness; (3) annealing the substrate, the passivation layer, the metal layer and the amorphous silicon layer at a temperature equal to or less than 600° C. and a period of time equal to or less than three hours to form a doped polysilicon layer below a residual metal layer; and (4) removing the residual metal layer to expose the doped polysilicon layer.Type: GrantFiled: June 24, 2013Date of Patent: April 14, 2015Assignee: Board of Regents, The University of Texas SystemInventors: Zeynep Celik-Butler, Suraj K. Patil, Donald Philip Butler
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Publication number: 20140091410Abstract: The present invention provides a method and apparatus for fabricating piezoresistive polysilicon on a substrate by low-temperature metal induced crystallization by: (1) providing the substrate having a passivation layer; (2) performing, at or near room temperature in a chamber without breaking a vacuum or near-vacuum within the chamber, the steps of: (a) creating a metal layer on the passivation layer, and (b) creating an amorphous silicon layer on the metal layer, wherein the metal layer and the amorphous silicon layer have approximately the same thickness; (3) annealing the substrate, the passivation layer, the metal layer and the amorphous silicon layer at a temperature equal to or less than 600° C. and a period of time equal to or less than three hours to form a doped polysilicon layer below a residual metal layer; and (4) removing the residual metal layer to expose the doped polysilicon layer.Type: ApplicationFiled: June 24, 2013Publication date: April 3, 2014Applicant: Board of Regents, The University of Texas SystemInventors: Zeynep Celik-Butler, Suraj K. Patil, Donald Philip Butler
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Patent number: 8492238Abstract: The present invention provides a method and apparatus for fabricating piezoresistive polysilicon on a substrate by low-temperature metal induced crystallization by: (1) providing the substrate having a passivation layer; (2) performing, at or near room temperature in a chamber without breaking a vacuum or near-vacuum within the chamber, the steps of: (a) creating a metal layer on the passivation layer, and (b) creating an amorphous silicon layer on the metal layer, wherein the metal layer and the amorphous silicon layer have approximately the same thickness; (3) annealing the substrate, the passivation layer, the metal layer and the amorphous silicon layer at a temperature equal to or less than 600° C. and a period of time equal to or less than three hours to form a doped polysilicon layer below a residual metal layer; and (4) removing the residual metal layer to expose the doped polysilicon layer.Type: GrantFiled: August 14, 2009Date of Patent: July 23, 2013Assignee: Board of Regents, The University of Texas SystemInventors: Zeynep Celik-Butler, Suraj K. Patil, Donald Philip Butler
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Publication number: 20100102403Abstract: The present invention provides a method and apparatus for fabricating piezoresistive polysilicon on a substrate by low-temperature metal induced crystallization by: (1) providing the substrate having a passivation layer; (2) performing, at or near room temperature in a chamber without breaking a vacuum or near-vacuum within the chamber, the steps of: (a) creating a metal layer on the passivation layer, and (b) creating an amorphous silicon layer on the metal layer, wherein the metal layer and the amorphous silicon layer have approximately the same thickness; (3) annealing the substrate, the passivation layer, the metal layer and the amorphous silicon layer at a temperature equal to or less than 600° C. and a period of time equal to or less than three hours to form a doped polysilicon layer below a residual metal layer; and (4) removing the residual metal layer to expose the doped polysilicon layer.Type: ApplicationFiled: August 14, 2009Publication date: April 29, 2010Applicant: BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEMInventors: Zeynep Celik-Butler, Suraj K. Patil, Donald Philip Butler