Patents by Inventor Susanne M. Balle

Susanne M. Balle has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240143410
    Abstract: Technologies for dividing work across one or more accelerator devices include a compute device. The compute device is to determine a configuration of each of multiple accelerator devices of the compute device, receive a job to be accelerated from a requester device remote from the compute device, and divide the job into multiple tasks for a parallelization of the multiple tasks among the one or more accelerator devices, as a function of a job analysis of the job and the configuration of each accelerator device. The compute engine is further to schedule the tasks to the one or more accelerator devices based on the job analysis and execute the tasks on the one or more accelerator devices for the parallelization of the multiple tasks to obtain an output of the job.
    Type: Application
    Filed: January 5, 2024
    Publication date: May 2, 2024
    Applicant: Intel Corporation
    Inventors: Susanne M. Balle, Francesc Guim Bernat, Slawomir Putyrski, Joe Grecco, Henry Mitchel, Evan Custodio, Rahul Khanna, Sujoy Sen
  • Publication number: 20240113954
    Abstract: Technologies for dynamically managing resources in disaggregated accelerators include an accelerator. The accelerator includes acceleration circuitry with multiple logic portions, each capable of executing a different workload. Additionally, the accelerator includes communication circuitry to receive a workload to be executed by a logic portion of the accelerator and a dynamic resource allocation logic unit to identify a resource utilization threshold associated with one or more shared resources of the accelerator to be used by a logic portion in the execution of the workload, limit, as a function of the resource utilization threshold, the utilization of the one or more shared resources by the logic portion as the logic portion executes the workload, and subsequently adjust the resource utilization threshold as the workload is executed. Other embodiments are also described and claimed.
    Type: Application
    Filed: November 9, 2023
    Publication date: April 4, 2024
    Inventors: Francesc GUIM BERNAT, Susanne M. BALLE, Rahul KHANNA, Sujoy SEN, Karthik KUMAR
  • Patent number: 11922227
    Abstract: Technologies for providing efficient migration of services include a server device. The server device includes compute engine circuitry to execute a set of services on behalf of a terminal device and migration accelerator circuitry. The migration accelerator circuitry is to determine whether execution of the services is to be migrated from an edge station in which the present server device is located to a second edge station in which a second server device is located, determine a prioritization of the services executed by the server device, and send, in response to a determination that the services are to be migrated and as a function of the determined prioritization, data utilized by each service to the second server device of the second edge station to migrate the services. Other embodiments are also described and claimed.
    Type: Grant
    Filed: December 21, 2022
    Date of Patent: March 5, 2024
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Karthik Kumar, Susanne M. Balle, Ignacio Astilleros Diez, Timothy Verrall, Ned M. Smith
  • Patent number: 11907557
    Abstract: Technologies for dividing work across one or more accelerator devices include a compute device. The compute device is to determine a configuration of each of multiple accelerator devices of the compute device, receive a job to be accelerated from a requester device remote from the compute device, and divide the job into multiple tasks for a parallelization of the multiple tasks among the one or more accelerator devices, as a function of a job analysis of the job and the configuration of each accelerator device. The compute engine is further to schedule the tasks to the one or more accelerator devices based on the job analysis and execute the tasks on the one or more accelerator devices for the parallelization of the multiple tasks to obtain an output of the job.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: February 20, 2024
    Assignee: Intel Corporation
    Inventors: Susanne M. Balle, Francesc Guim Bernat, Slawomir Putyrski, Joe Grecco, Henry Mitchel, Evan Custodio, Rahul Khanna, Sujoy Sen
  • Patent number: 11861424
    Abstract: Technologies for providing efficient reprovisioning in an accelerator device include an accelerator sled. The accelerator sled includes a memory and an accelerator device coupled to the memory. The accelerator device is to configure itself with a first bit stream to establish a first kernel, execute the first kernel to produce output data, write the output data to the memory, configure itself with a second bit stream to establish a second kernel, and execute the second kernel with the output data in the memory used as input data to the second kernel. Other embodiments are also described and claimed.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: January 2, 2024
    Assignee: Intel Corporation
    Inventors: Evan Custodio, Susanne M. Balle, Francesc Guim Bernat, Slawomir Putyrski, Joe Grecco, Henry Mitchel
  • Patent number: 11855766
    Abstract: Technologies for dynamically managing resources in disaggregated accelerators include an accelerator. The accelerator includes acceleration circuitry with multiple logic portions, each capable of executing a different workload. Additionally, the accelerator includes communication circuitry to receive a workload to be executed by a logic portion of the accelerator and a dynamic resource allocation logic unit to identify a resource utilization threshold associated with one or more shared resources of the accelerator to be used by a logic portion in the execution of the workload, limit, as a function of the resource utilization threshold, the utilization of the one or more shared resources by the logic portion as the logic portion executes the workload, and subsequently adjust the resource utilization threshold as the workload is executed. Other embodiments are also described and claimed.
    Type: Grant
    Filed: April 29, 2022
    Date of Patent: December 26, 2023
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Susanne M. Balle, Rahul Khanna, Sujoy Sen, Karthik Kumar
  • Publication number: 20230359743
    Abstract: Disclosed herein are embodiments related to security in cloudlet environments. In some embodiments, for example, a computing device (e.g., a cloudlet) may include: a trusted execution environment; a Basic Input/Output System (BIOS) to request a Key Encryption Key (KEK) from the trusted execution environment; and a Self-Encrypting Storage (SES) associated with the KEK; wherein the trusted execution environment is to verify the BIOS and provide the KEK to the BIOS subsequent to verification of the BIOS, and the BIOS is to provide the KEK to the SES to unlock the SES for access by the trusted execution environment.
    Type: Application
    Filed: July 18, 2023
    Publication date: November 9, 2023
    Applicant: Intel Corporation
    Inventors: Yeluri Raghuram, Susanne M. Balle, Nigel Thomas Cook, Kapil Sood
  • Publication number: 20230344894
    Abstract: An apparatus is described. The apparatus includes a host side interface to couple to one or more central processing units (CPUs) that support multiple microservice endpoints. The apparatus includes a network interface to receive from a network a packet having multiple frames that belong to different streams, the multiple frames formatted according to a text transfer protocol. The apparatus includes circuitry to: process the frames according to the text transfer protocol and build content of a microservice functional call embedded within a message that one of the frames transports; and, execute the microservice function call.
    Type: Application
    Filed: June 29, 2023
    Publication date: October 26, 2023
    Inventors: Susanne M. BALLE, Shihwei CHIEN, Andrzej KURIATA, Nagabhushan CHITLUR
  • Publication number: 20230325265
    Abstract: A network interface device connects to one or more endpoint devices and a network. The network interface device receives packet from the network and parses the packet to determine characteristics of the packet, where the packet includes serialized data according to a serialization format. Based on the characteristics, the network interface device determines whether data within the packet can be deserialized using data transformation acceleration hardware provided on the network interface device and which of a plurality of sub-protocols of a multiprotocol interconnect are to be utilized to transport the data to a destination device in the one or more endpoint devices.
    Type: Application
    Filed: June 13, 2023
    Publication date: October 12, 2023
    Inventors: Susanne M. Balle, Duane Galbi, Shihwei Roger Chien, Nagabhushan Chitlur, Andrzej Kuriata
  • Patent number: 11748486
    Abstract: Disclosed herein are embodiments related to security in cloudlet environments. In some embodiments, for example, a computing device (e.g., a cloudlet) may include: a trusted execution environment; a Basic Input/Output System (BIOS) to request a Key Encryption Key (KEK) from the trusted execution environment; and a Self-Encrypting Storage (SES) associated with the KEK; wherein the trusted execution environment is to verify the BIOS and provide the KEK to the BIOS subsequent to verification of the BIOS, and the BIOS is to provide the KEK to the SES to unlock the SES for access by the trusted execution environment.
    Type: Grant
    Filed: October 7, 2021
    Date of Patent: September 5, 2023
    Assignee: Intel Corporation
    Inventors: Yeluri Raghuram, Susanne M. Balle, Nigel Thomas Cook, Kapil Sood
  • Patent number: 11695668
    Abstract: Technologies for allocating resources of managed nodes to workloads to balance multiple resource allocation objectives include an orchestrator server to receive resource allocation objective data indicative of multiple resource allocation objectives to be satisfied. The orchestrator server is additionally to determine an initial assignment of a set of workloads among the managed nodes and receive telemetry data from the managed nodes. The orchestrator server is further to determine, as a function of the telemetry data and the resource allocation objective data, an adjustment to the assignment of the workloads to increase an achievement of at least one of the resource allocation objectives without decreasing an achievement of another of the resource allocation objectives, and apply the adjustments to the assignments of the workloads among the managed nodes as the workloads are performed. Other embodiments are also described and claimed.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: July 4, 2023
    Assignee: Intel Corporation
    Inventors: Susanne M. Balle, Rahul Khanna, Nishi Ahuja, Mrittika Ganguli
  • Publication number: 20230205604
    Abstract: Technologies for providing efficient migration of services include a server device. The server device includes compute engine circuitry to execute a set of services on behalf of a terminal device and migration accelerator circuitry. The migration accelerator circuitry is to determine whether execution of the services is to be migrated from an edge station in which the present server device is located to a second edge station in which a second server device is located, determine a prioritization of the services executed by the server device, and send, in response to a determination that the services are to be migrated and as a function of the determined prioritization, data utilized by each service to the second server device of the second edge station to migrate the services. Other embodiments are also described and claimed.
    Type: Application
    Filed: December 21, 2022
    Publication date: June 29, 2023
    Inventors: Francesc Guim Bernat, Karthik Kumar, Susanne M. Balle, Ignacio Astilleros Diez, Timothy Verrall, Ned M. Smith
  • Publication number: 20230195346
    Abstract: A compute device to manage workflow to disaggregated computing resources is provided. The compute device comprises a compute engine receive a workload processing request, the workload processing request defined by at least one request parameter, determine at least one accelerator device capable of processing a workload in accordance with the at least one request parameter, transmit a workload to the at least one accelerator device, receive a work product produced by the at least one accelerator device from the workload, and provide the work product to an application.
    Type: Application
    Filed: February 14, 2023
    Publication date: June 22, 2023
    Applicant: Intel Corporation
    Inventors: Francesc Guim Bernat, Evan Custodio, Susanne M. Balle, Joe Grecco, Henry Mitchel, Slawomir Putyrski
  • Publication number: 20230185760
    Abstract: Methods, apparatus, and software and for hardware microservices accelerated in other processing units (XPUs). The apparatus may be a platform including a System on Chip (SOC) and an XPU, such as a Field Programmable Gate Array (FPGA). The FPGA is configured to implement one or more Hardware (HW) accelerator functions associated with HW microservices. Execution of microservices is split between a software front-end that executes on the SOC and a hardware backend comprising the HW accelerator functions. The software front-end offloads a portion of a microservice and/or associated workload to the HW microservice backend implemented by the accelerator functions. An XPU or FPGA proxy is used to provide the microservice front-ends with shared access to HW accelerator functions, and schedules/multiplexes access to the HW accelerator functions using, e.g., telemetry data generated by the microservice front-ends and/or the HW accelerator functions.
    Type: Application
    Filed: December 13, 2021
    Publication date: June 15, 2023
    Inventors: Susanne M. BALLE, Duane E. GALBI, Andrzej KURIATA, Sundar NADATHUR, Nagabhushan CHITLUR, Francesc GUIM BERNAT, Alexander BACHMUTSKY
  • Patent number: 11604882
    Abstract: Disclosed herein are embodiments related to security in cloudlet environments. In some embodiments, for example, a computing device (e.g., a cloudlet) may include: a trusted execution environment; a Basic Input/Output System (BIOS) to request a Key Encryption Key (KEK) from the trusted execution environment; and a Self-Encrypting Storage (SES) associated with the KEK; wherein the trusted execution environment is to verify the BIOS and provide the KEK to the BIOS subsequent to verification of the BIOS, and the BIOS is to provide the KEK to the SES to unlock the SES for access by the trusted execution environment.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: March 14, 2023
    Assignee: Intel Corporation
    Inventors: Yeluri Raghuram, Susanne M. Balle, Nigel Thomas Cook, Kapil Sood
  • Patent number: 11579788
    Abstract: Technologies for providing shared memory for accelerator sleds includes an accelerator sled to receive, with a memory controller, a memory access request from an accelerator device to access a region of memory. The request is to identify the region of memory with a logical address. Additionally, the accelerator sled is to determine from a map of logical addresses and associated physical address, the physical address associated with the region of memory. In addition, the accelerator sled is to route the memory access request to a memory device associated with the determined physical address.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: February 14, 2023
    Assignee: Intel Corporation
    Inventors: Henry Mitchel, Joe Grecco, Sujoy Sen, Francesc Guim Bernat, Susanne M. Balle, Evan Custodio, Paul Dormitzer
  • Patent number: 11573900
    Abstract: Examples described herein relate to prefetching content from a remote memory device to a memory tier local to a higher level cache or memory. An application or device can indicate a time availability for data to be available in a higher level cache or memory. A prefetcher used by a network interface can allocate resources in any intermediary network device in a data path from the remote memory device to the memory tier local to the higher level cache. Memory access bandwidth, egress bandwidth, memory space in any intermediary network device can be allocated for prefetch of content. In some examples, proactive prefetch can occur for content expected to be prefetched but not requested to be prefetched.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: February 7, 2023
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Slawomir Putyrski, Susanne M. Balle
  • Publication number: 20230029026
    Abstract: A network processing device connects to one or more devices in a computing node and connects to one or more other network processing devices of other computing nodes. The network processing device identifies a policy for allowing devices in other computing nodes to access a particular resource of one of the devices in its computing node. The network processing device receives an access request to access the particular resource from another network processing device and sends a request to the device hosting the particular resource based on the access request and the policy.
    Type: Application
    Filed: September 30, 2022
    Publication date: January 26, 2023
    Applicant: Intel Corporation
    Inventors: Francesc Guim Bernat, Karthik Kumar, Susanne M. Balle, Andrzej Kuriata, Duane Galbi
  • Publication number: 20230023229
    Abstract: In a server system, a host computing platform can have a processing unit separate from the host processor to detect and respond to failure of the host processor. The host computing platform includes a memory to store data for the host processor. The processing unit has an interface to the host processor and the memory and an interface to a network external to the host processor and has access to the memory. In response to detection of failure of the host processor, the processing unit migrates data from the memory to another memory or storage.
    Type: Application
    Filed: September 26, 2022
    Publication date: January 26, 2023
    Inventors: Karthik KUMAR, Francesc GUIM BERNAT, Alexander BACHMUTSKY, Susanne M. BALLE, Andrzej KURIATA, Nagabhushan CHITLUR
  • Patent number: 11537447
    Abstract: Technologies for providing efficient migration of services include a server device. The server device includes compute engine circuitry to execute a set of services on behalf of a terminal device and migration accelerator circuitry. The migration accelerator circuitry is to determine whether execution of the services is to be migrated from an edge station in which the present server device is located to a second edge station in which a second server device is located, determine a prioritization of the services executed by the server device, and send, in response to a determination that the services are to be migrated and as a function of the determined prioritization, data utilized by each service to the second server device of the second edge station to migrate the services. Other embodiments are also described and claimed.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: December 27, 2022
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Karthik Kumar, Susanne M. Balle, Ignacio Astilleros Diez, Timothy Verrall, Ned M. Smith