Patents by Inventor Susumu Iwamoto
Susumu Iwamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20100022075Abstract: An active region in a semiconductor device is made up of a parallel p-n layer including a first p-semiconductor layer and a first n-semiconductor with the widths and total amounts of impurities being equal to each other to provide a structure in which charges are balanced. A section parallel to stripes in the parallel p-n layer in an inactive region is made up of a second parallel p-n layer including a second p-semiconductor layer, with its width larger than that of the first p-semiconductor layer, and a second n-semiconductor layer with its width smaller than that of the first n-semiconductor layer. The total amount of impurities in the second p-semiconductor layer is made larger than that in the second n-semiconductor layer to provide a structure in which charges are made unbalanced.Type: ApplicationFiled: September 29, 2009Publication date: January 28, 2010Applicant: FUJI ELECTRIC HOLDINGS CO., LTD.Inventors: Kouta TAKAHASHI, Susumu IWAMOTO
-
Patent number: 7605061Abstract: An active region in a semiconductor device is made up of a parallel p-n layer including a first p-semiconductor layer and a first n-semiconductor with the widths and total amounts of impurities being equal to each other to provide a structure in which charges are balanced. A section parallel to stripes in the parallel p-n layer in an inactive region is made up of a second parallel p-n layer including a second p-semiconductor layer, with its width larger than that of the first p-semiconductor layer, and a second n-semiconductor layer with its width smaller than that of the first n-semiconductor layer. The total amount of impurities in the second p-semiconductor layer is made larger than that in the second n-semiconductor layer to provide a structure in which charges are made unbalanced.Type: GrantFiled: May 8, 2007Date of Patent: October 20, 2009Assignee: Fuji Electric Holdings Co., Ltd.Inventors: Kouta Takahashi, Susumu Iwamoto
-
Publication number: 20090194786Abstract: A semiconductor device includes deep first field limiting rings, shallow second field limiting rings, insulation films covering each surface portion of each of the first and the second field limiting rings, and conductive field plates each in contact with a surface of each of the first and the second field limiting rings. Each of the field plates project over a surface of each of the insulation films between the first field limiting rings and the second field limiting rings.Type: ApplicationFiled: February 3, 2009Publication date: August 6, 2009Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.Inventors: Susumu IWAMOTO, Takashi KOBAYASHI
-
Patent number: 7355257Abstract: A semiconductor superjunction device has a superjunction structure formed in a drift region of the device. The superjunction structure has alternately arranged n-type regions and p-type semiconductor regions layered parallel with the drift direction of carriers, permitting current flow when turned ON and depleting when turned OFF. It also includes a first intrinsic semiconductor region between the n-type and p-type regions. The first intrinsic semiconductor region and the n-type and p-type regions sandwiching the first intrinsic semiconductor region forming a unit. A plurality of units are repetitively arranged to form a repetitively arranged structure. The value of mobility of one of electrons in the n-type region or holes in the p-type region is equal to or less than half the value of mobility of corresponding to one of electrons or holes in the first intrinsic semiconductor region.Type: GrantFiled: March 8, 2006Date of Patent: April 8, 2008Assignee: Fuji Electric Holdings Co., Ltd.Inventors: Daisuke Kishimoto, Susumu Iwamoto, Katsunori Ueno
-
Publication number: 20070207597Abstract: An active region in a semiconductor device is made up of a parallel p-n layer including a first p-semiconductor layer and a first n-semiconductor with the widths and total amounts of impurities being equal to each other to provide a structure in which charges are balanced. A section parallel to stripes in the parallel p-n layer in an inactive region is made up of a second parallel p-n layer including a second p-semiconductor layer, with its width larger than that of the first p-semiconductor layer, and a second n-semiconductor layer with its width smaller than that of the first n-semiconductor layer. The total amount of impurities in the second p-semiconductor layer is made larger than that in the second n-semiconductor layer to provide a structure in which charges are made unbalanced.Type: ApplicationFiled: May 8, 2007Publication date: September 6, 2007Applicant: Fuji Electric Holdings Co., Ltd.Inventors: Kouta Takahashi, Susumu Iwamoto
-
Patent number: 7262459Abstract: An active region in a semiconductor device is made up of a parallel p-n layer including a first p-semiconductor layer and a first n-semiconductor with the widths and total amounts of impurities being equal to each other to provide a structure in which charges are balanced. A section parallel to stripes in the parallel p-n layer in an inactive region is made up of a second parallel p-n layer including a second p-semiconductor layer, with its width larger than that of the first p-semiconductor layer, and a second n-semiconductor layer with its width smaller than that of the first n-semiconductor layer. The total amount of impurities in the second p-semiconductor layer is made larger than that in the second n-semiconductor layer to provide a structure in which charges are made unbalanced.Type: GrantFiled: February 9, 2005Date of Patent: August 28, 2007Assignee: Fuji Electric Holdings Co., Ltd.Inventors: Kouta Takahashi, Susumu Iwamoto
-
Publication number: 20060256487Abstract: A semiconductor superjunction device has a superjunction structure formed in a drift region of the device. The superjunction structure has alternately arranged n-type regions and p-type semiconductor regions layered parallel with the drift direction of carriers, permitting current flow when turned ON and depleting when turned OFF. It also includes a first intrinsic semiconductor region between the n-type and p-type regions. The first intrinsic semiconductor region and the n-type and p-type regions sandwiching the first intrinsic semiconductor region forming a unit. A plurality of units are repetitively arranged to form a repetitively arranged structure. The value of mobility of one of electrons in the n-type region or holes in the p-type region is equal to or less than half the value of mobility of corresponding to one of electrons or holes in the first intrinsic semiconductor region.Type: ApplicationFiled: March 8, 2006Publication date: November 16, 2006Applicant: FUJI ELECTRIC HOLDING CO., LTD.Inventors: Daisuke Kishimoto, Susumu Iwamoto, Katsunori Ueno
-
Patent number: 7042046Abstract: Disclosed is a semiconductor device facilitating a peripheral portion thereof with a breakdown voltage higher than the breakdown voltage in the drain drift layer without employing a guard ring or field plate. A preferred embodiment includes a drain drift region with a first alternating conductivity type layer formed of n drift current path regions and p partition regions arranged alternately with each other, and a breakdown withstanding region with a second alternating conductivity type layer formed of n regions and p regions arranged alternately with each other, the breakdown withstanding region providing no current path in the ON-state of the device and being depleted in the OFF-state of the device. Since depletion layers expand in both directions from multiple pn-junctions into n regions and p regions in the OFF-state of the device, the adjacent areas of p-type base regions, the outer area of the semiconductor chip and the deep area of the semiconductor chip are depleted.Type: GrantFiled: August 25, 2004Date of Patent: May 9, 2006Assignee: Fuji Electric Device Technology Co., Ltd.Inventors: Yasuhiko Onishi, Tatsuhiko Fujihira, Katsunori Ueno, Susumu Iwamoto, Takahiro Sato, Tatsuji Nagaoka
-
Patent number: 7029977Abstract: A fabrication method of a semiconductor wafer can fill trenches formed in a semiconductor substrate with an epitaxial film with high crystal quality without leaving cavities in the trenches. The trenches are formed in the first conductivity type semiconductor substrate. Planes exposed inside the trenches are made clean surfaces by placing the substrate in a gas furnace, followed by supplying the furnace with an etching gas and carrier gas, and by performing etching on the exposed planes inside the trenches by a thickness from about a few nanometers to one micrometer. The trenches have a geometry opening upward through the etching. Following the etching, a second conductivity type semiconductor is epitaxially grown in the trenches by supplying the furnace with a growth gas, etching gas, doping gas and carrier gas, thereby filling the trenches. Instead of making the trenches slightly-opened upward, their sidewalls may be made planes enabling facet formation.Type: GrantFiled: March 5, 2004Date of Patent: April 18, 2006Assignees: Fuji Electric Holdings Co., Ltd., Shin-Etsu Handotai Co., Ltd.Inventors: Daisuke Kishimoto, Susumu Iwamoto, Katsunori Ueno, Ryohsuke Shimizu, Satoshi Oka
-
Patent number: 7002211Abstract: A lateral semiconductor device includes an alternating conductivity type layer for providing a first semiconductor current path in the ON-state of the device and for being depleted in the OFF-state of the device, that has an improved structure for realizing a high breakdown voltage in the curved sections of the alternating conductivity type layer.Type: GrantFiled: May 19, 2004Date of Patent: February 21, 2006Assignee: Fuji Electric Co., Ltd.Inventors: Yasuhiko Onishi, Tatsuhiko Fujihira, Susumu Iwamoto, Takahiro Sato
-
Patent number: 7002205Abstract: Disclosed is a semiconductor device facilitating a peripheral portion thereof with a breakdown voltage higher than the breakdown voltage in the drain drift layer without employing a guard ring or field plate. A preferred embodiment includes a drain drift region with a first alternating conductivity type layer formed of n drift current path regions and p partition regions arranged alternately with each other, and a breakdown withstanding region with a second alternating conductivity type layer formed of n regions and p regions arranged alternately with each other, the breakdown withstanding region providing no current path in the ON-state of the device and being depleted in the OFF-state of the device. Since depletion layers expand in both directions from multiple pn-junctions into n regions and p regions in the OFF-state of the device, the adjacent areas of p-type base regions, the outer area of the semiconductor chip and the deep area of the semiconductor chip are depleted.Type: GrantFiled: December 12, 2003Date of Patent: February 21, 2006Assignee: Fuji Electric Device Technology Co., Ltd.Inventors: Yasuhiko Onishi, Tatsuhiko Fujihira, Katsunori Ueno, Susumu Iwamoto, Takahiro Sato, Tatsuji Nagaoka
-
Publication number: 20050184336Abstract: An active region in a semiconductor device is made up of a parallel p-n layer including a first p-semiconductor layer and a first n-semiconductor with the widths and total amounts of impurities being equal to each other to provide a structure in which charges are balanced. A section parallel to stripes in the parallel p-n layer in an inactive region is made up of a second parallel p-n layer including a second p-semiconductor layer, with its width larger than that of the first p-semiconductor layer, and a second n-semiconductor layer with its width smaller than that of the first n-semiconductor layer. The total amount of impurities in the second p-semiconductor layer is made larger than that in the second n-semiconductor layer to provide a structure in which charges are made unbalanced.Type: ApplicationFiled: February 9, 2005Publication date: August 25, 2005Applicant: Fuji Electric Holdings Co., Ltd.Inventors: Kouta Takahashi, Susumu Iwamoto
-
Patent number: 6903418Abstract: A semiconductor device facilitates obtaining a higher breakdown voltage in the portion of the semiconductor chip around the drain drift region and improving the avalanche withstanding capability thereof. A vertical MOSFET according to the invention includes a drain layer; a drain drift region on drain layer, drain drift region including a first alternating conductivity type layer; a breakdown withstanding region (the peripheral region of the semiconductor chip) on drain layer and around drain drift region, breakdown withstanding region providing substantially no current path in the ON-state of the MOSFET, breakdown withstanding region being depleted in the OFF-state of the MOSFET, breakdown withstanding region including a second alternating conductivity type layer, and an under region below a gate pad, and the under region including a third alternating conductivity type layer.Type: GrantFiled: October 3, 2003Date of Patent: June 7, 2005Assignee: Fuji Electric Device Technology Co., Ltd.Inventors: Susumu Iwamoto, Tatsuhiko Fujihira, Katsunori Ueno, Yasuhiko Onishi, Takahiro Sato, Tatsuji Nagaoka
-
Patent number: 6900109Abstract: A semiconductor device includes an improved drain drift layer structure of alternating conductivity types, that is easy to manufacture, and that facilitates realizing a high current capacity and a high breakdown voltage and to provide a method of manufacturing the semiconductor device. The vertical MOSFET according to the invention includes an alternating-conductivity-type drain drift layer on an n+-type drain layer as a substrate. The alternating-conductivity-type drain drift layer is formed of n-type drift current path regions and p-type partition regions alternately arranged laterally with each other. The n-type drift current path regions and p-type partition regions extend in perpendicular to n+-type drain layer. Each p-type partition region is formed by vertically connecting p-type buried diffusion unit regions Up. The n-type drift current path regions are residual regions, left after connecting p-type buried diffusion unit regions Up, with the conductivity type thereof unchanged.Type: GrantFiled: February 28, 2003Date of Patent: May 31, 2005Assignee: Fuji Electric Co., Ltd.Inventors: Yasuhiko Onishi, Tatsuhiko Fujihira, Susumu Iwamoto, Takahiro Sato
-
Publication number: 20050017292Abstract: Disclosed is a semiconductor device facilitating a peripheral portion thereof with a breakdown voltage higher than the breakdown voltage in the drain drift layer without employing a guard ring or field plate. A preferred embodiment includes a drain drift region with a first alternating conductivity type layer formed of n drift current path regions and p partition regions arranged alternately with each other, and a breakdown withstanding region with a second alternating conductivity type layer formed of n regions and p regions arranged alternately with each other, the breakdown withstanding region providing no current path in the ON-state of the device and being depleted in the OFF-state of the device. Since depletion layers expand in both directions from multiple pn-junctions into n regions and p regions in the OFF-state of the device, the adjacent areas of p-type base regions, the outer area of the semiconductor chip and the deep area of the semiconductor chip are depleted.Type: ApplicationFiled: August 25, 2004Publication date: January 27, 2005Inventors: Yasuhiko Onishi, Tatsuhiko Fujihira, Katsunori Ueno, Susumu Iwamoto, Takahiro Sato, Tatsuji Nagaoka
-
Patent number: 6825537Abstract: In a trench super junction semiconductor element having a parallel p-n junction layer 14 with n-drift regions 12 and p-partition regions 13, both extending in a depth direction, being alternately joined, a part 20 in a shape of a three-dimensional curved surface in the end portion of each of trenches is formed in a p-partition region 13. A section in the p-partition region 13 surrounding the part 20 in a shape of a three-dimensional curved surface of the end portion of each of the trenches is made as a p+-region 21 in which an impurity concentration is higher than that in a section thereunder so that an electric field is increased at a boundary between the p+-region 21 and the n-drift region 12, thereby lessening electric field concentration to the part 20 in a shape of a three-dimensional curved surface of the end portion of the trench.Type: GrantFiled: October 10, 2003Date of Patent: November 30, 2004Assignee: Fuji Electric Device Technology Co., Ltd.Inventors: Susumu Iwamoto, Yasuhiko Onishi, Takahiro Sato, Tatsuji Nagaoka
-
Patent number: 6825565Abstract: A semiconductor device includes a drift region, which includes a first alternating conductivity type layer, and a peripheral region, which includes a second alternating conductivity type layer and a third alternating conductivity type layer in the surface portion of the peripheral region. The first layer includes first n-type regions and first p-type regions arranged alternately at a first pitch. The second layer is continuous with the first layer and includes second n-type regions and second p-type regions arranged alternately at the first pitch. The impurity concentration in the second layer is almost the same as the impurity concentration in the first layer. The third layer includes third n-type regions and third p-type regions arranged alternately at a second pitch. The third layer can be doped more lightly than the first and second alternating conductivity type layers. The second pitch can be the same as the first pitch or smaller.Type: GrantFiled: January 30, 2003Date of Patent: November 30, 2004Assignee: Fuji Electric Co., Ltd.Inventors: Yasuhiko Onishi, Tatsuji Nagaoka, Susumu Iwamoto, Takahiro Sato
-
Publication number: 20040212032Abstract: A lateral semiconductor device includes an alternating conductivity type layer for providing a first semiconductor current path in the ON-state of the device and for being depleted in the OFF-state of the device, that has an improved structure for realizing a high breakdown voltage in the curved sections of the alternating conductivity type layer.Type: ApplicationFiled: May 19, 2004Publication date: October 28, 2004Applicant: Fuji Electric Co., Ltd.Inventors: Yasuhiko Onishi, Tatsuhiko Fujihira, Susumu Iwamoto, Takahiro Sato
-
Publication number: 20040185665Abstract: A fabrication method of a semiconductor wafer can fill trenches formed in a semiconductor substrate with an epitaxial film with high crystal quality without leaving cavities in the trenches. The trenches are formed in the first conductivity type semiconductor substrate. Planes exposed inside the trenches are made clean surfaces by placing the substrate in a gas furnace, followed by supplying the furnace with an etching gas and carrier gas, and by performing etching on the exposed planes inside the trenches by a thickness from about a few nanometers to one micrometer. The trenches have a geometry opening upward through the etching. Following the etching, a second conductivity type semiconductor is epitaxially grown in the trenches by supplying the furnace with a growth gas, etching gas, doping gas and carrier gas, thereby filling the trenches. Instead of making the trenches slightly-opened upward, their sidewalls may be made planes enabling facet formation.Type: ApplicationFiled: March 5, 2004Publication date: September 23, 2004Applicants: FUJI ELECTRIC HOLDINGS CO., LTD., SHIN-ETSU HANDOTAI CO., LTD.Inventors: Daisuke Kishimoto, Susumu Iwamoto, Katsunori Ueno, Ryosuke Shimizu, Satoshi Oka
-
Patent number: 6787420Abstract: This invention clarifies the effects of parameters and enables the mass production of a super-junction semiconductor device, which has a drift layer composed of a parallel pn layer that conducts electricity in the ON state and is depleted in the OFF state. The quantity of impurities in n drift regions is within the range between 100% and 150% or between 110% and 150% of the quantity of impurities in p partition regions. The impurity density of either one of the n drift regions and the p partition regions is within the range between 92% and 108% of the impurity density of the other regions. In addition, the width of either one of the n drift regions and the p partition regions is within the range between 94% and 106% of the width of the other regions.Type: GrantFiled: July 16, 2001Date of Patent: September 7, 2004Assignee: Fuji Electric Co., Ltd.Inventors: Yasushi Miyasaka, Tatsuhiko Fujihira, Yasuhiko Ohnishi, Katsunori Ueno, Susumu Iwamoto