Abstract: High-speed data communication devices, e.g., repeaters, interfacing between a host and a peripheral operate such that high-speed components except for a host-side squelch detector are set or maintained in a deactivated state during an idle period of a micro frame. In an example, a start of a micro frame is detected on a data bus during a first time period. In a second time period after the first time period, the high-speed communication device determines whether at least one data packet is contained in the micro frame. When it is determined during the second time period that no data packet is contained in the micro frame, active components, except a squelch detector, are controlled to be inactive during a third time period after the second time period.

Abstract: A method includes determining a charging port mode by receiving a data contact detect (DCD) Complete signal, reducing a voltage on a first data pin of a Universal Serial Bus (USB) connector of a portable device, and determining that a condition is true when a voltage on a second data pin of the USB connector is equal to or greater than 0.8 to 2.0 Volts (V), and is false otherwise. When the condition is true, a first signal is sent on a control circuit output indicating indicate that the PD is connected to a dedicated charging port (DCP) of Divider 0 mode. When the condition is false, a second signal is sent on the control circuit output indicating that the PD is connected to a DCP of 1.2V short mode.

Abstract: High-speed data communication devices, e.g., repeaters, interfacing between a host and a peripheral operate such that high-speed components except for a host-side squelch detector are set or maintained in a deactivated state during an idle period of a micro frame. In an example, a start of a micro frame is detected on a data bus during a first time period. In a second time period after the first time period, the high-speed communication device determines whether at least one data packet is contained in the micro frame. When it is determined during the second time period that no data packet is contained in the micro frame, active components, except a squelch detector, are controlled to be inactive during a third time period after the second time period.

Abstract: At least some aspects of the present disclosure provide for a method. In some examples, the method includes receiving 2-line data in an embedded Universal Serial Bus (eUSB) format. The method further includes encoding the 2-line data into a single signal. The single signal comprises a first symbol corresponding to a first state change of the 2-line data and a second symbol corresponding to a second state change of the 2-line data.

Abstract: A system for selecting an equalizer setting of an equalizer to equalize signals received via a communications link. Starting with a first (e.g., minimum) equalizer setting and a threshold voltage near the mid-eye voltage of the equalized output signal, the system estimates the amplitude of the inner eye of the equalized output signal by comparing the equalized output signal to a series of threshold voltages. If the amplitude of the equalized output signal is less than ideal, the system dynamically increases the equalizer setting. The system quickly converges on the equalizer setting for the communication link because, rather than comparing the output signal at every voltage offset using every equalizer setting, the system only evaluates the equalizer settings necessary to select the equalizer setting for the communications link and uses only the voltage offsets necessary to evaluate each equalizer setting.

Abstract: This disclosure generally relates to USB TYPE-C, and, in particular, DISPLAYPORT Alternate Mode communication in a USB TYPE-C environment. In one embodiment, a device determines a DISPLAYPORT mode and determines an orientation of a USB TYPE-C connector plug. A multiplexer multiplexes a DISPLAYPORT transmission based in part on the determined orientation of the USB TYPE-C connector plug.

Abstract: At least some aspects of the present disclosure provide for a method. In some examples, the method includes receiving 2-line data in an embedded Universal Serial Bus (eUSB) format. The method further includes encoding the 2-line data into a single signal. The single signal comprises a first symbol corresponding to a first state change of the 2-line data and a second symbol corresponding to a second state change of the 2-line data.

Abstract: This disclosure generally relates to USB TYPE-C, and, in particular, DISPLAYPORT Alternate Mode communication in a USB TYPE-C environment. In one embodiment, a device determines a DISPLAYPORT mode and determines an orientation of a USB TYPE-C connector plug. A multiplexer multiplexes a DISPLAYPORT transmission based in part on the determined orientation of the USB TYPE-C connector plug.

Abstract: A system for selecting an equalizer setting of an equalizer to equalize signals received via a communications link. Starting with a first (e.g., minimum) equalizer setting and a threshold voltage near the mid-eye voltage of the equalized output signal, the system estimates the amplitude of the inner eye of the equalized output signal by comparing the equalized output signal to a series of threshold voltages. If the amplitude of the equalized output signal is less than ideal, the system dynamically increases the equalizer setting. The system quickly converges on the equalizer setting for the communication link because, rather than comparing the output signal at every voltage offset using every equalizer setting, the system only evaluates the equalizer settings necessary to select the equalizer setting for the communications link and uses only the voltage offsets necessary to evaluate each equalizer setting.

Abstract: A serial bus signal conditioner circuit includes receiver circuitry, a mode identification circuit, and an edge-rate booster circuit. The receiver circuitry is configured to receive signals transmitted on a serial bus. The mode identification circuit is coupled to the receiver circuitry, and is configured to identify initiation of or return to high-speed signaling on the serial bus based on sequences of the signals transmitted on the serial bus. The edge-rate booster circuit is coupled to the mode identification circuit, and is configured to identify edges of a differential signal transmitted on the serial bus, and to supply a differential current to the serial bus based on identification of an edge of the differential signal.

Abstract: In an example, a data communication device includes one or more receivers, and one or more transmitters. The data communication device detects a start of frame packet (?SOF) on a data bus, wherein the ?SOF indicates the start of a microframe; determines whether there are any data packets contained in the microframe during a first threshold period after the ?SOF; and detects that there is no data packet contained in the microframe during the first threshold period after the ?SOF, and in response, transitions at least one of the one or more transmitters from an active state to an OFF state, and transitions the at least one of the one or more transmitters from the OFF state to the active state prior to a switchback period before the end of the microframe.

Abstract: A system for selecting an equalizer setting of an equalizer to equalize signals received via a communications link. Starting with a first (e.g., minimum) equalizer setting and a threshold voltage near the mid-eye voltage of the equalized output signal, the system estimates the amplitude of the inner eye of the equalized output signal by comparing the equalized output signal to a series of threshold voltages. If the amplitude of the equalized output signal is less than ideal, the system dynamically increases the equalizer setting. The system quickly converges on the equalizer setting for the communication link because, rather than comparing the output signal at every voltage offset using every equalizer setting, the system only evaluates the equalizer settings necessary to select the equalizer setting for the communications link and uses only the voltage offsets necessary to evaluate each equalizer setting.

Abstract: A serial bus repeater includes first and second ports adapted to be coupled to respective devices. A first termination resistor network couples to the first port. A second termination resistor network couples to the second port. A squelch detect circuit couples to the first bus port and is configured to detect activity on the first bus and to generate a squelch signal responsive to detection of activity on the first port. A first state machine is configured to: determine an elapsed time during which the squelch signal indicates activity on the first port; determine that the elapsed time exceeds a first threshold; and, responsive to the determination that the elapsed time exceeds the first threshold, assert configuration signals to reconfigure the first and second termination resistor networks.

Abstract: Aspects of the disclosure provide for a method. In at least some examples, the method includes receiving, at a circuit, data via a differential input signal. The method further includes detecting a falling edge in the data received via the differential input signal. The method further includes holding an output of the circuit at a final logical value of the data. The method further includes disabling a transmitter of the circuit while holding the output of the circuit at the final logical value of the data. The method further includes releasing the output of the circuit from the final logical value of the data.

Abstract: A circuit includes signal conditioner circuitry, level shifter circuitry, and state detector and controller circuitry coupled between the signal conditioner circuitry and the level shifter circuitry. The state detector and controller circuitry includes receiver circuitry and a finite state machine coupled to the receiver circuitry. The finite state machine is configured to detect a first data rate from signals, control operation of the signal conditioner circuitry responsive to detecting the first data rate, and control operation of the level shifter circuitry during a second data rate.

Abstract: At least some aspects of the present disclosure provide for a method. In some examples, the method includes receiving, at a circuit, data via a differential input signal, detecting a rising edge in the data received via the differential input signal, and precharging a common mode voltage (Vcm) node of the differential input signal responsive to detecting the rising edge in the data received via the differential input signal, wherein the Vcm node is a floating node.

Abstract: A method of operating an embedded universal serial bus (eUSB) repeater includes holding an eUSB receiver and a USB transmitter in active states and holding a USB receiver and an eUSB transmitter in standby states. The method includes receiving by the eUSB receiver a token packet indicative of transmission of a first downstream packet, and transitioning the USB receiver and the eUSB transmitter from the standby states to the active states responsive to the token packet. The method includes transmitting the token packet by the USB transmitter. The method includes receiving by the eUSB receiver a downstream packet or receiving by the USB receiver an upstream packet within a first timeout period after receiving the token packet, and transmitting the downstream packet by the USB transmitter or transmitting the upstream packet by the eUSB transmitter.

Abstract: High-speed data communication devices, e.g., repeaters, interfacing between a host and a peripheral operate such that high-speed components except for a host-side squelch detector are set or maintained in a deactivated state during an idle period of a micro frame. In an example, a start of a micro frame is detected on a data bus during a first time period. In a second time period after the first time period, the high-speed communication device determines whether at least one data packet is contained in the micro frame. When it is determined during the second time period that no data packet is contained in the micro frame, active components, except a squelch detector, are controlled to be inactive during a third time period after the second time period.

Abstract: In an example, a data communication device includes one or more receivers, and one or more transmitters. The data communication device detects a start of frame packet (?SOF) on a data bus, wherein the ?SOF indicates the start of a microframe; determines whether there are any data packets contained in the microframe during a first threshold period after the ?SOF; and detects that there is no data packet contained in the microframe during the first threshold period after the ?SOF, and in response, transitions at least one of the one or more transmitters from an active state to an OFF state, and transitions the at least one of the one or more transmitters from the OFF state to the active state prior to a switchback period before the end of the microframe.

Abstract: A circuit includes signal conditioner circuitry, level shifter circuitry, and state detector and controller circuitry coupled between the signal conditioner circuitry and the level shifter circuitry. The state detector and controller circuitry includes receiver circuitry and a finite state machine coupled to the receiver circuitry. The finite state machine is configured to detect a first data rate from signals, control operation of the signal conditioner circuitry responsive to detecting the first data rate, and control operation of the level shifter circuitry during a second data rate.