Patents by Inventor Syouji Nogami
Syouji Nogami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10379094Abstract: A contamination control method includes: a wafer loading step for loading a monitor wafer in a chamber of a vapor deposition apparatus; a heat-treatment repetition step for consecutively repeating a heat-treatment step for thermally treating the monitor wafer for predetermined times; a wafer unloading step for unloading the monitor wafer from the chamber; and a wafer-contamination-evaluation step for evaluating a metal-contamination degree of the monitor wafer unloaded out of the chamber. The heat-treatment step includes a first heat-treatment step for thermally treating the monitor wafer in an atmosphere of a hydrogen-containing gas and a second heat-treatment step for thermally treating the monitor wafer in an atmosphere of a hydrogen-chloride-containing gas and the hydrogen-containing gas.Type: GrantFiled: September 17, 2015Date of Patent: August 13, 2019Assignee: SUMCO CORPORATIONInventor: Syouji Nogami
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Publication number: 20160097144Abstract: A contamination control method includes: a wafer loading step for loading a monitor wafer in a chamber of a vapor deposition apparatus; a heat-treatment repetition step for consecutively repeating a heat-treatment step for thermally treating the monitor wafer for predetermined times; a wafer unloading step for unloading the monitor wafer from the chamber; and a wafer-contamination-evaluation step for evaluating a metal-contamination degree of the monitor wafer unloaded out of the chamber. The heat-treatment step includes a first heat-treatment step for thermally treating the monitor wafer in an atmosphere of a hydrogen-containing gas and a second heat-treatment step for thermally treating the monitor wafer in an atmosphere of a hydrogen-chloride-containing gas and the hydrogen-containing gas.Type: ApplicationFiled: September 17, 2015Publication date: April 7, 2016Applicant: SUMCO CORPORATIONInventor: Syouji NOGAMI
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Patent number: 9034721Abstract: A semiconductor substrate is provided in which an alignment mark is formed that can be used for an alignment even after the formation of an impurity diffused layer by the planarization of an epitaxial film. A trench is formed in an alignment region of an N?-type layer formed on an N+-type substrate. This trench is used to leave voids after the formation of a P?-type epitaxial film on the N?-type layer. Then, the voids formed in the N?-type layer can be used as an alignment mark. Thus, such a semiconductor substrate can be used to provide an alignment in the subsequent step of manufacturing the semiconductor apparatus. Thus, the respective components constituting the semiconductor apparatus can be formed at desired positions accurately.Type: GrantFiled: July 31, 2014Date of Patent: May 19, 2015Assignees: SUMCO CORPORATION, DENSO CORPORATIONInventors: Syouji Nogami, Tomonori Yamaoka, Shoichi Yamauchi, Nobuhiro Tsuji, Toshiyuki Morishita
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Patent number: 8956947Abstract: A semiconductor substrate is provided in which an alignment mark is formed that can be used for an alignment even after the formation of an impurity diffused layer by the planarization of an epitaxial film. A trench is formed in an alignment region of an N?-type layer formed on an N+-type substrate. This trench is used to leave voids after the formation of a P?-type epitaxial film on the N?-type layer. Then, the voids formed in the N?-type layer can be used as an alignment mark. Thus, such a semiconductor substrate can be used to provide an alignment in the subsequent step of manufacturing the semiconductor apparatus. Thus, the respective components constituting the semiconductor apparatus can be formed at desired positions accurately.Type: GrantFiled: July 31, 2014Date of Patent: February 17, 2015Assignees: Sumco Corporation, Denso CorporationInventors: Syouji Nogami, Tomonori Yamaoka, Shoichi Yamauchi, Nobuhiro Tsuji, Toshiyuki Morishita
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Publication number: 20140342535Abstract: A semiconductor substrate preventing a void from being generated in an epitaxial film buried in a trench. An N-type first epitaxial film and first trenches are formed on an N+-type substrate body. A P-type second epitaxial film is buried in the first trenches. An N+-type third epitaxial film having the same composition as the first epitaxial film is formed on the first and second epitaxial films to form second trenches. A fourth epitaxial film is grown on the entire interior of the second trenches. The formation of the first and second trenches and the burying of the second and fourth epitaxial films are performed in a plurality of steps. Thus, the aspect ratio of the first and second trenches when the second and fourth epitaxial films are buried can be reduced. As a result, the second and fourth epitaxial films can be buried in the first and second trenches without causing a void.Type: ApplicationFiled: July 31, 2014Publication date: November 20, 2014Inventors: Syouji NOGAMI, Tomonori YAMAOKA, Shoichi YAMAUCHI, Nobuhiro TSUJI, Toshiyuki MORISHITA
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Publication number: 20140342525Abstract: A semiconductor substrate is provided in which an alignment mark is formed that can be used for an alignment even after the formation of an impurity diffused layer by the planarization of an epitaxial film. A trench is formed in an alignment region of an N?-type layer formed on an N+-type substrate. This trench is used to leave voids after the formation of a P?-type epitaxial film on the N?-type layer. Then, the voids formed in the N?-type layer can be used as an alignment mark. Thus, such a semiconductor substrate can be used to provide an alignment in the subsequent step of manufacturing the semiconductor apparatus. Thus, the respective components constituting the semiconductor apparatus can be formed at desired positions accurately.Type: ApplicationFiled: July 31, 2014Publication date: November 20, 2014Inventors: Syouji NOGAMI, Tomonori YAMAOKA, Shoichi YAMAUCHI, Nobuhiro TSUJI, Toshiyuki MORISHITA
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Publication number: 20140342526Abstract: A semiconductor substrate is provided in which an alignment mark is formed that can be used for an alignment even after the formation of an impurity diffused layer by the planarization of an epitaxial film. A trench is formed in an alignment region of an N?-type layer formed on an N+-type substrate. This trench is used to leave voids after the formation of a P?-type epitaxial film on the N?-type layer. Then, the voids formed in the N?-type layer can be used as an alignment mark. Thus, such a semiconductor substrate can be used to provide an alignment in the subsequent step of manufacturing the semiconductor apparatus. Thus, the respective components constituting the semiconductor apparatus can be formed at desired positions accurately.Type: ApplicationFiled: July 31, 2014Publication date: November 20, 2014Inventors: Syouji NOGAMI, Tomonori YAMAOKA, Shoichi YAMAUCHI, Nobuhiro TSUJI, Toshiyuki MORISHITA
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Patent number: 8835276Abstract: A semiconductor substrate is provided in which an alignment mark is formed that can be used for an alignment even after the formation of an impurity diffused layer by the planarization of an epitaxial film. A trench is formed in an alignment region of an N+-type substrate. This trench is used to leave voids after the formation of an N?-type layer. Then, the voids formed in the N+-type substrate can be used as an alignment mark. Thus, such a semiconductor substrate can be used to provide an alignment in the subsequent step of manufacturing the semiconductor apparatus. Thus, the respective components constituting the semiconductor apparatus can be formed at desired positions accurately.Type: GrantFiled: December 9, 2010Date of Patent: September 16, 2014Assignees: Sumco Corporation, Denso CorporationInventors: Syouji Nogami, Tomonori Yamaoka, Shoichi Yamauchi, Nobuhiro Tsuji, Toshiyuki Morishita
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Patent number: 8501598Abstract: A semiconductor substrate which allows desired electrical characteristics to be more easily acquired, a semiconductor device of the same, and a method of producing the semiconductor substrate. The method of producing this semiconductor substrate is provided with: a first epitaxial layer forming step (S1) of forming a first epitaxial layer; a trench forming step (S2) of forming trenches in the first epitaxial layer; and epitaxial layer forming steps (S3, S4, S5) of forming epitaxial layers on the first epitaxial layer and inside the trenches, using a plurality of growth conditions including differing growth rates, so as to fill the trenches, and keeping the concentration of dopant taken into the epitaxial layers constant in the plurality of growth conditions.Type: GrantFiled: March 25, 2010Date of Patent: August 6, 2013Assignees: Sumco Corporation, Denso CorporationInventors: Syouji Nogami, Hitoshi Goto, Takumi Shibata, Tsuyoshi Yamamoto
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Publication number: 20120032312Abstract: A semiconductor substrate which allows desired electrical characteristics to be more easily acquired, a semiconductor device of the same, and a method of producing the semiconductor substrate. The method of producing this semiconductor substrate is provided with: a first epitaxial layer forming step (S1) of forming a first epitaxial layer; a trench forming step (S2) of forming trenches in the first epitaxial layer; and epitaxial layer forming steps (S3, S4, S5) of forming epitaxial layers on the first epitaxial layer and inside the trenches, using a plurality of growth conditions including differing growth rates, so as to fill the trenches, and keeping the concentration of dopant taken into the epitaxial layers constant in the plurality of growth conditions.Type: ApplicationFiled: March 25, 2010Publication date: February 9, 2012Applicants: DENSO CORPORATION, SUMCO CORPORATIONInventors: Syouji Nogami, Hitoshi Goto, Takumi Shibata, Tsuyoshi Yamamoto
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Patent number: 8097511Abstract: A semiconductor device is provided, which includes a substrate; a P-N column layer disposed on the substrate; a second conductivity type epitaxial layer disposed on the P-N column layer. The P-N column layer includes first conductivity type columns and second conductivity type columns, which are alternately arranged. Each column has a tapered shape. A portion of the first conductivity type column located around the substrate has a smaller impurity concentration than another portion of the first conductivity type column located around the second conductivity type epitaxial layer. A portion of the second conductivity type column located around the substrate has a larger impurity concentration than another portion of the first conductivity type column located around the second conductivity type epitaxial layer.Type: GrantFiled: June 5, 2008Date of Patent: January 17, 2012Assignees: Denso Corporation, Sumco CorporationInventors: Takumi Shibata, Shouichi Yamauchi, Syouji Nogami, Tomonori Yamaoka
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Publication number: 20110076830Abstract: A semiconductor substrate is provided in which an alignment mark is formed that can be used for an aligment even after the formation of an impurity diffused layer by the planarization of an epitaxial film. A trench is formed in an alignment region of an N+-type substrate. This trench is used to leave voids after the formation of an N?-type layer. Then, the voids formed in the N+-type substrate can be used as an alignment mark. Thus, such a semiconductor substrate can be used to provide an alignment in the subsequent step of manufacturing the semiconductor apparatus. Thus, the respective components constituting the semiconductor apparatus can be formed at desired positions accurately.Type: ApplicationFiled: December 9, 2010Publication date: March 31, 2011Applicants: SUMCO CORPORATION, DENSO CORPORATIONInventors: Syouji NOGAMI, Tomonori YAMAOKA, Shoichi YAMAUCHI, Nobuhiro TSUJI, Toshiyuki MORISHITA
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Patent number: 7811907Abstract: A method for manufacturing a semiconductor device includes steps of: forming a trench on a main surface of a silicon substrate; forming a first epitaxial film on the main surface and in the trench; and forming a second epitaxial film on the first epitaxial film. The step of forming the first epitaxial film has a first process condition with a first growth rate of the first epitaxial film. The step of forming the second epitaxial film has a second process condition with a second growth rate of the second epitaxial film. The second growth rate is larger than the first growth rate.Type: GrantFiled: September 28, 2006Date of Patent: October 12, 2010Assignees: DENSO CORPORATION, Sumco CorporationInventors: Takumi Shibata, Shoichi Yamauchi, Tomonori Yamaoka, Syouji Nogami
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Patent number: 7776710Abstract: A resistivity of an epitaxial layer in a trench is changed in a stepwise manner by reducing a quantity of an impurity diffused into the epitaxial layer in the trench from a semiconductor wafer in a stepwise manner, thereby suppressing an influence of auto-doping from the semiconductor wafer. An epitaxial layer 17 is grown in a trench 16 of a semiconductor wafer 10 having a trench structure by gradually reducing a temperature in a temperature in the range of 400 to 1150° C. by a vapor growth method while supplying a silane gas as a raw material gas, thereby filling the epitaxial layer 17 in the trench 16.Type: GrantFiled: March 31, 2005Date of Patent: August 17, 2010Assignees: Sumco Corporation, Denso CorporationInventors: Syouji Nogami, Yukichi Horioka, Shoichi Yamauchi
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Patent number: 7642178Abstract: A method for manufacturing a semiconductor device includes steps of: forming a first epitaxial film on a silicon substrate; forming a trench in the first epitaxial film; and forming a second epitaxial film on the first epitaxial film and in the trench. The step of forming the second epitaxial film includes a final step, in which a mixed gas of a silicon source gas and a halide gas is used. The silicon substrate has an arsenic concentration defined as ?. The second epitaxial film has an impurity concentration defined as ?. The arsenic concentration and the impurity concentration has a relationship of: ??3×1019×ln(?)?1×1021.Type: GrantFiled: September 26, 2006Date of Patent: January 5, 2010Assignees: DENSO CORPORATION, Sumco CorporationInventors: Shoichi Yamauchi, Takumi Shibata, Tomonori Yamaoka, Syouji Nogami
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Publication number: 20090273102Abstract: A semiconductor substrate is provided in which an alignment mark is formed that can be used for an aligment even after the formation of an impurity diffused layer by the planarization of an epitaxial film. A trench 11 is formed in an alignment region of an N+-type substrate 1. This trench 11 is used to leave voids 3 after the formation of an N?-type layer 2. Then, the voids 3 formed in the N+-type substrate 1 can be used as an alignment mark. Thus, such a semiconductor substrate can be used to provide an alignment in the subsequent step of manufacturing the semiconductor apparatus. Thus, the respective components constituting the semiconductor apparatus can be formed at desired positions accurately.Type: ApplicationFiled: October 5, 2006Publication date: November 5, 2009Inventors: Syouji Nogami, Tomonori Yamaoka, Shoichi Yamauchi, Nobuhiro Tsuji, Toshiyuki Morishita
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Patent number: 7601603Abstract: A method for manufacturing a semiconductor device includes the steps of: forming a trench in a semiconductor substrate; and forming an epitaxial film on the substrate including a sidewall and a bottom of the trench so that the epitaxial film is filled in the trench. The step of forming the epitaxial film includes a final step before the trench is filled with the epitaxial film. The final step has a forming condition of the epitaxial film in such a manner that the epitaxial film to be formed on the sidewall of the trench has a growth rate at an opening of the trench smaller than a growth rate at a position of the trench, which is deeper than the opening of the trench.Type: GrantFiled: March 31, 2005Date of Patent: October 13, 2009Assignees: DENSO CORPORATION, Sumitomo Mitsubishi Silicon CorporationInventors: Shoichi Yamauchi, Hitoshi Yamaguchi, Tomoatsu Makino, Syouji Nogami, Tomonori Yamaoka
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Publication number: 20080303114Abstract: A semiconductor device is provided, which includes a substrate; a P-N column layer disposed on the substrate; a second conductivity type epitaxial layer disposed on the P-N column layer. The P-N column layer includes first conductivity type columns and second conductivity type columns, which are alternately arranged. Each column has a tapered shape. A portion of the first conductivity type column located around the substrate has a smaller impurity concentration than another portion of the first conductivity type column located around the second conductivity type epitaxial layer. A portion of the second conductivity type column located around the substrate has a larger impurity concentration than another portion of the first conductivity type column located around the second conductivity type epitaxial layer.Type: ApplicationFiled: June 5, 2008Publication date: December 11, 2008Applicants: DENSO CORPORATION, SUMCO CORPORATIONInventors: Takumi Shibata, Shouichi Yamauchi, Syouji Nogami, Tomonori Yamaoka
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Patent number: 7364980Abstract: Closure at the opening of a trench with an epitaxial film is restrained, and thereby, filling morphology in the trenches is improved. A method for manufacturing a semiconductor substrate includes a step for growing an epitaxial layer 11 on the surface of a silicon substrate 13, a step of forming a trench 14 in this epitaxial layer, and a step of filling the inside of the trench 14 with the epitaxial film 12, wherein mixed gas made by mixing halogenoid gas into silicon source gas is circulated as material gas in filling the inside of the trench with the epitaxial film, and when the standard flow rate of the halogenoid gas is defined as Xslm and the film formation speed of the epitaxial film formed by the circulation of the silicon source gas is defined as Y?m/min, in the case when the aspect ratio of the trench is less than 10, an expression Y<0.2X+0.10 is satisfied, and in the case that the aspect ratio of the trench is between 10 and less than 20, an expression Y<0.2X+0.Type: GrantFiled: October 6, 2006Date of Patent: April 29, 2008Assignees: Sumco Corporation, Denso CorporationInventors: Syouji Nogami, Tomonori Yamaoka, Shoichi Yamauchi, Hitoshi Yamaguchi, Takumi Shibata
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Patent number: RE44236Abstract: A method for manufacturing a semiconductor device includes the steps of: forming a trench in a semiconductor substrate; and forming an epitaxial film on the substrate including a sidewall and a bottom of the trench so that the epitaxial film is filled in the trench. The step of forming the epitaxial film includes a final step before the trench is filled with the epitaxial film. The final step has a forming condition of the epitaxial film in such a manner that the epitaxial film to be formed on the sidewall of the trench has a growth rate at an opening of the trench smaller than a growth rate at a position of the trench, which is deeper than the opening of the trench.Type: GrantFiled: October 12, 2011Date of Patent: May 21, 2013Assignees: DENSO CORPORATION, Sumco CorporationInventors: Shoichi Yamauchi, Hitoshi Yamaguchi, Tomoatsu Makino, Syouji Nogami, Tomonori Yamaoka