Abstract: For a memory array, a main data bus commonly used for first and second data bit widths, and a main data bus used only for the second data bit width are disposed. According to a data bit width, connection between memory blocks and main data lines is switched. The main data buses are connected to write/read circuits, and expanding/compressing operation on data bits is performed by an expansion/compression circuit in a unit of a predetermined number of bits. Thus, with the same configuration irrespective of data bit width, compression of data bits in the multi-bit test can be performed to output the compression result to the same data terminal.

Abstract: A bias voltage having a positive temperature dependency is supplied to a current source that determines the operating current of a refresh timer that issues a refresh request to allow the driving current of the current source to have a positive temperature characteristic. In this manner, the refresh cycle of the refresh timer shortens the issue intervals when the temperature rises, and lengthens the issue intervals of the refresh request when the temperature decreases. Thus, the consumed current for the refresh at room temperature is reduced. Consequently, the consumed current in a self-refresh mode under the room temperature condition can be reduced.

Abstract: In the output circuit, at a subsequent stage of a gate circuit operating with a power supply voltage related to a first power supply voltage, a latch circuit formed of an inverter circuit and a MOS transistor is arranged, and is supplied with a second power supply voltage as an operating power supply voltage. An output buffer circuit is driven in accordance with an output signal of the latch circuit. When the first power supply voltage is powered down, the latch circuit receiving and operating with the second power supply voltage holds a signal voltage to be attained in a standby state and thus the output buffer circuit is reliably held in an output high impedance state. In a semiconductor device of a double power supply configuration, even when one power supply is powered down, the output buffer circuit can reliably be set to an output high impedance state.

Abstract: Pad lines are placed on the peripheral region of a chip along EAST band and WEST band (E/W band). In order to allow the chip with pads arranged on the peripheral region to be adaptable to a TSOP, VDD and VSS pads are arranged on the edge region on NORTH band and SOUTH band (N/S band) near the center of the N/S band. Moreover, in consideration of frame design for the TSOP, some pads on the ends of the pad lines among the pads included in the pad lines are arranged in reverse order relative to the order of pins. Further, VDDQ and VSSQ pads are arranged in the same order as that of pins for a package which requires no consideration of frame design. On the other hand, for use in a BGA package, VDD and VSS pads are arranged in pairs at respective ends of the pad lines. A semiconductor memory device with this pad arrangement is accordingly adaptable to various types of packages.

Abstract: A repeater circuit, operative in response to a clock signal transmitted from an internal clock generation circuit on a clock signal line, outputs one of first and second clock signals depending on whether a CAS latency of one or that of two is applied. The first clock signal pulses twice for activation within the period of an external clock. An input/output circuit, for the CAS latency of no less than two, stores read data in response to the second clock signal attaining the active state, and for the CAS latency of one, stores read data in response to the first clock signal and an equalization signal each attaining the active state.

Abstract: In a low power consumption mode, an internal power supply circuit produces an internal power supply voltage by electrically coupling an internal power supply line to either an external power supply line or a ground line through a transistor. Accordingly, in the low power consumption mode, supply of an operating current to a reference voltage generation circuit, a buffer circuit, an internal power supply voltage generation circuit and a voltage booster circuit is discontinued, allowing for reduction in power consumption of the internal power supply circuit itself.

Abstract: In a low power consumption mode, an internal power supply circuit produces an internal power supply voltage by electrically coupling an internal power supply line to either an external power supply line or a ground line through a transistor. Accordingly, in the low power consumption mode, supply of an operating current to a reference voltage generation circuit, a buffer circuit, an internal power supply voltage generation circuit and a voltage booster circuit is discontinued, allowing for reduction in power consumption of the internal power supply circuit itself.

Abstract: A repeater circuit, operative in response to a clock signal transmitted from an internal clock generation circuit on a clock signal line, outputs one of first and second clock signals depending on whether a CAS latency of one or that of two is applied. The first clock signal pulses twice for activation within the period of an external clock. An input/output circuit for the CAS latency of no less than two stores read data in response the second clock signal attaining the active state and for the CAS latency of one stores read data in response to the first clock signal and an equalization signal each attaining the active state.

Abstract: In a control circuit and an address buffer circuit, buffer circuits of plural types are provided to each of pin terminals and an input buffer of one type is activated according a state control signal group. In a standby state, current paths of the control buffer circuit and the address buffer circuit are selectively cut off according to a CS cut mode instructing signal stored in a mode register and an internal chip select signal. Furthermore, when a low power consumption mode is specified, a current path of a CLK buffer for generating an internal clock signal is cut off according to an external clock enable signal and a low power mode instructing signal, and the current paths of the control buffer circuit and the address buffer circuit are also cut-off.

Abstract: Data specifying details of refresh to be executed in the self-refresh mode is stored in a register circuit in a mode register. A refresh period and refresh region are determined according to data stored in register circuit and a refresh control circuit generates a control signal and a refresh address that are required for refresh. Stored data can be stably held in the self-refresh mode in which data holding is performed with reduced current consumption.

Abstract: Data for switching a slew rate of a data output circuit included in a data input/output circuit between a slew rate in a normal mode and a slow slew rate is stored in a mode register. According to the data stored in mode register, a slew rate setting signal is generated. According to a slew rate switching circuit, the slew rate of the data input/output circuit is switched between a slew rate in the normal mode and a slow slew rate slower than the slew rate in the normal mode. A data output circuit is achieved which occupies a small area, is capable of setting a slew rate slower than the slew rate in a normal mode and outputting data without causing an erroneous operation with a low consumption current even when the slew rate is adjusted.

Abstract: A control signal generation circuit according to the present invention includes a plurality of control circuits supplying different internal control signals as outputs, respectively, and a common delay circuit. The common delay circuit includes a plurality of delay circuits for delaying a control signal serving as a reference. These delay circuits are connected in series and output signals of respective delay circuits can be taken out through taps provided corresponding thereto. Each of the plurality of control circuits sets a signal level of a corresponding internal control signal according to the change in a signal level of a corresponding tap.

Abstract: A control signal generation circuit according to the present invention includes a plurality of control circuits supplying different internal control signals as outputs, respectively, and a common delay circuit. The common delay circuit includes a plurality of delay circuits for delaying a control signal serving as a reference. These delay circuits are connected in series and output signals of respective delay circuits can be taken out through taps provided corresponding thereto. Each of the plurality of control circuits sets a signal level of a corresponding internal control signal according to the change in a signal level of a corresponding tap.

Abstract: In a bit line reference potential (VBL) generating circuit, a pad is connected via a transfer gate to a reference node in a reference stage. During a device evaluation test, the transfer gate is turned on in response to a test signal so that a voltage is applied to the reference node with a tester driver via the pad to control a potential of an output node in an output stage. Thus, the semiconductor memory device is capable of stably controlling the bit line reference potential VBL regardless of the drivability of the tester driver during the device evaluation test.

Abstract: A semiconductor integrated circuit includes a first bank, a first input/output circuit, a second bank, a second input/output circuit, a data bus, and a plurality of circuits. The first and second banks are each divided into four blocks. Data buses formed of data buses for inputting/outputting data to/from a memory cell included in each block are arranged to cross at points A, B, C between adjacent two circuits of the plurality of circuits. Consequently, the area occupied by the data buses can be made smaller.

Abstract: A semiconductor device includes a PMOS transistor and an NMOS transistor. In a standby state, a potential of Vcc level is applied to the substrate of the PMOS transistor and a potential of Vss level is applied to the substrate of the NMOS transistor. Therefore, the voltage between the source and substrate of the P and NMOS transistors becomes 0 V. In an active state, potentials that render the voltage between the source and substrate lower than the built-in potential are applied to respective substrates of the P and NMOS transistors. Therefore, the threshold voltage of the transistor is lowered in an active state than in a standby state, and almost no leakage current flows between the source and substrate.

Abstract: An interface circuit performs supply/reception of data with a register instead of supply/reception of data with DRAM when an area specified by an address signal is a logic control area. Data signals in the case are a control command for a logic circuit held in a register and input data to be processed. The logic circuit takes charge of a critical path in processing time such as cryptographic processing and image processing. A processing result is held in the register. The register circuit switches between storage data stored in DRAM and data given from a terminal group to select data to be processed according to a control signal.

Abstract: If a region designated by an address signal is a logic control region, an interface portion transmits/receives data to/from a register instead of a DRAM. A data signal used at that time is a control command for a logic circuit held in the register or input data for a process in the logic circuit. Depending on the content held in the register, the logic circuit performs, for example, an encryption process or a process which takes for a microcomputer a long time to complete such as an image processing. The result of processing is stored in the register and read in a sequence of reading from the DRAM.

Abstract: A semiconductor integrated circuit includes a first bank, a first input/output circuit, a second bank, a second input/output circuit, a data bus, and a plurality of circuits. The first and second banks are each divided into four blocks. Data buses formed of data buses for inputting/outputting data to/from a memory cell included in each block are arranged to cross at points A, B, C between adjacent two circuits of the plurality of circuits. Consequently, the area occupied by the data buses can be made smaller.

Abstract: A semiconductor memory device converts an automatic precharge signal, which is an asynchronous control signal, to a synchronous signal and inhibits a synchronous control circuit from an operation with respect to an illegal command in response to the converted signal. An internal malfunction with respect to the illegal command can be prevented due to this structure.