Abstract: A device and a device manufacturing process. First, a gettering layer is formed on the bottom surface of a silicon substrate. Gates having a MOS structure are then formed on the principal surface of the silicon substrate, and the gettering layer is removed. According to this manufacturing method, the formation of the gates having a MOS structure is performed such that the gettering layer getters dissolved oxygen present in the silicon substrate. This reduces the concentration of dissolved oxygen in the silicon substrate, resulting in improved device characteristics.

Abstract: In a MOSFET using SiC a p-type channel is formed by epitaxial growth, so that the depletion layer produced in the p-type region right under the channel is reduced, even when the device is formed in a self-aligned manner. Thus, a high breakdown voltage is obtained. Also, since the device is formed in a self-aligned manner, the device size can be reduced so that an increased number of devices can be fabricated in a certain area and the on-state resistance can be reduced.

Abstract: A semiconductor substrate has a trench in a first main surface. An insulated gate field effect part includes a gate electrode formed in the first main surface. A potential fixing electrode fills the trench and has an expanding part expanding on the first main surface so that a width thereof is larger than the width of the trench. An emitter electrode is formed on the first main surface and insulated from the gate electrode electrically and connected to a whole upper surface of the expanding part of the potential fixing electrode. Thus, a semiconductor device capable of enhancing reliability in order to prevent an aluminum spike from generating and a manufacturing method thereof can be provided.

Abstract: A pin diode is formed by a p+ collector region, an n type buffer region, an n? region and an n+ cathode region. A trench is formed from the surface of n+ cathode region through n+ cathode region to reach n? region. An insulating film is formed along an inner wall surface of trench. A gate electrode layer is formed to oppose to the sidewall of n+ cathode region with insulating film interposed. A cathode electrode is formed to be electrically connected to n+ cathode region. An anode electrode is formed to be electrically connected to p+ collector region. The n+ cathode region is formed entirely over the surface between trenches extending parallel to each other. Thus, a power semiconductor device in which gate control circuit is simplified and which has good on property can be obtained.

Abstract: A semiconductor device of the present invention has a pn-repeating structure that a structure in which a p-type impurity region (4) and an n-type drift region (3) are aligned side by side is repeated twice or more, and a low concentration region which is either p-type impurity region (4) or n-type drift region (3) located at the outermost portion of this pn-repeating structure has the lowest impurity concentration or has the least generally effective charge amount among all the p-type impurity regions (4) and n-type drift regions (3) forming the pn-repeating structure.

Abstract: A semiconductor device that includes an insulating substrate, a plurality of semiconductor layers arranged to be isolated from one another on the insulating substrate, and a semiconductor element independently provided on the semiconductor layers. Further, a trench may extend from the main surface to the substrate and have an inner wall covered with an insulating film. At least one of an edge on the side of the substrate and an edge on the side opposite thereof of the semiconductor layer has a rounded surface. Further, an angle between a line tangent to a surface having a smallest radius of curvature of the rounded surface of the edge and the main surface ranges from 30° to 60° at a section of the edge.

Abstract: A semiconductor device includes an n-type semiconductor substrate (1) including a p-type collector layer (2) formed in a second main surface side thereof, a trench (13) is formed in a peripheral portion of the semiconductor substrate (1) so as to surround the inside and reach the collector layer (2) from a first main surface of the semiconductor substrate (1), and a p-type isolation region (14) formed by diffusion from a sidewall of the trench (13) is provided to be connected to the collector layer (2). The trench (13) is filled with a filling material (16).

Abstract: The semiconductor device of the present invention has a repeat structure of repeated unit structures in a semiconductor substrate (1), each unit structure having an n type diffusion region (3) and a p type diffusion region (4) in contact with each other to form a pn junction sandwiched between trenches (1a). An impurity amount in the n type diffusion region (3) and an impurity amount in the p type diffusion region (4) in the unit structure are set unequal (or different). Thus, in the semiconductor device having the trenches (1a), favorable breakdown voltage and avalanche breakdown tolerance can be ensured at the same time.

Abstract: A pin diode is formed by a p+ collector region, an n type buffer region, an n? region and an n+ cathode region. A trench is formed from the surface of n+ cathode region through n+ cathode region to reach n? region. An insulating film is formed along an inner wall surface of trench. A gate electrode layer is formed to oppose to the sidewall of n+ cathode region with insulating film interposed. A cathode electrode is formed to be electrically connected to n+ cathode region. An anode electrode is formed to be electrically connected to p+ collector region. The n+ cathode region is formed entirely over the surface between trenches extending parallel to each other. Thus, a power semiconductor device in which gate control circuit is simplified and which has good on property can be obtained.

Abstract: A pin diode is formed by a p+ collector region, an n type buffer region, an n? region and an n+ cathode region. A trench is formed from the surface of n+ cathode region through n+ cathode region to reach n? region. An insulating film is formed along an inner wall surface of trench. A gate electrode layer is formed to oppose to the sidewall of n+ cathode region with insulating film interposed. A cathode electrode is formed to be electrically connected to n+ cathode region. An anode electrode is formed to be electrically connected to p+ collector region. The n+ cathode region is formed entirely over the surface between trenches extending parallel to each other. Thus, a power semiconductor device in which gate control circuit is simplified and which has good on property can be obtained.

Abstract: A pin diode is formed by a p+ collector region, an n type buffer region, an n? region and an n+ cathode region. A trench is formed from the surface of n+ cathode region through n+ cathode region to reach n? region. An insulating film is formed along an inner wall surface of trench. A gate electrode layer is formed to oppose to the sidewall of n+ cathode region with insulating film interposed. A cathode electrode is formed to be electrically connected to n+ cathode region. An anode electrode is formed to be electrically connected to p+ collector region. The n+ cathode region is formed entirely over the surface between trenches extending parallel to each other. Thus, a power semiconductor device in which gate control circuit is simplified and which has good on property can be obtained.

Abstract: A semiconductor device of the present invention has a pn-repeating structure that a structure in which a p-type impurity region (4) and an n-type drift region (3) are aligned side by side is repeated twice or more, and a low concentration region which is either p-type impurity region (4) or n-type drift region (3) located at the outermost portion of this pn-repeating structure has the lowest impurity concentration or has the least generally effective charge amount among all the p-type impurity regions (4) and n-type drift regions (3) forming the pn-repeating structure.

Abstract: A semiconductor device includes an n-type semiconductor substrate (1) including a p-type collector layer (2) formed in a second main surface side thereof, a trench (13) is formed in a peripheral portion of the semiconductor substrate (1) so as to surround the inside and reach the collector layer (2) from a first main surface of the semiconductor substrate (1), and a p-type isolation region (14) formed by diffusion from a sidewall of the trench (13) is provided to be connected to the collector layer (2). The trench (13) is filled with a filling material (16).

Abstract: A semiconductor device of the present invention has a pn-repeating structure that a structure in which a p-type impurity region (4) and an n-type drift region (3) are aligned side by side is repeated twice or more, and a low concentration region which is either p-type impurity region (4) or n-type drift region (3) located at the outermost portion of this pn-repeating structure has the lowest impurity concentration or has the least generally effective charge amount among all the p-type impurity regions (4) and n-type drift regions (3) forming the pn-repeating structure.

Abstract: The semiconductor device of the present invention has a repeat structure of repeated unit structures in a semiconductor substrate (1), each unit structure having an n type diffusion region (3) and a p type diffusion region (4) in contact with each other to form a pn junction sandwiched between trenches (1a). An impurity amount in the n type diffusion region (3) and an impurity amount in the p type diffusion region (4) in the unit structure are set unequal (or different). Thus, in the semiconductor device having the trenches (1a), favorable breakdown voltage and avalanche breakdown tolerance can be ensured at the same time.

Abstract: A semiconductor device which includes a substrate made of a semiconductor having a main surface. A trench is selectively formed in the substrate at a predetermined depth from the main surface. An insulating film is formed at an inner wall of the trench. A control electrode layer fills an inside of the trench through the insulating film. An insulating layer protrudes from the main surface on the control electrode layer. At least one of an edge of an opening of the trench and a bottom of the trench has a rounded surface.

Abstract: A pin diode is formed by a p+ collector region, an n type buffer region, an n− region and an n+ cathode region. A trench is formed from the surface of n+ cathode region through n+ cathode region to reach n− region. An insulating film is formed along an inner wall surface of trench. A gate electrode layer is formed to oppose to the sidewall of n+ cathode region with insulating film interposed. A cathode electrode is formed to be electrically connected to n+ cathode region. An anode electrode is formed to be electrically connected to p+ collector region. The n+ cathode region is formed entirely over the surface between trenches extending parallel to each other. Thus, a power semiconductor device in which gate control circuit is simplified and which has good on property can be obtained.

Abstract: There is disclosed a method of fabricating a semiconductor device which includes the steps of forming a trench (4), and repeating the formation and removal of an oxide film (a sacrificial oxide film) twice to provide a rounded configuration (5b) of an opening portion of the trench (4) and a rounded configuration (6b) of a bottom thereof and to draw defects in a semiconductor layer into a silicon oxide film (8), reducing the defects adjacent the inner wall of the trench (4), whereby electric field concentration on a gate is prevented and the mobility of carriers in channels is improved for an improvement in characteristic, particularly an on-state voltage, of a power device. (FIG.

Abstract: A pin diode is formed by a p+ collector region, an n type buffer region, an n− region and an n+ cathode region. A trench is formed from the surface of n+ cathode region through n+ cathode region to reach n− region. An insulating film is formed along an inner wall surface of trench. A gate electrode layer is formed to oppose to the sidewall of n+ cathode region with insulating film interposed. A cathode electrode is formed to be electrically connected to n+ cathode region. An anode electrode is formed to be electrically connected to p+ collector region. The n+ cathode region is formed entirely over the surface between trenches extending parallel to each other. Thus, a power semiconductor device in which gate control circuit is simplified and which has good on property can be obtained.

Abstract: A semiconductor device of the present invention has a pn-repeating structure that a structure in which a p-type impurity region (4) and an n-type drift region (3) are aligned side by side is repeated twice or more, and a low concentration region which is either p-type impurity region (4) or n-type drift region (3) located at the outermost portion of this pn-repeating structure has the lowest impurity concentration or has the least generally effective charge amount among all the p-type impurity regions (4) and n-type drift regions (3) forming the pn-repeating structure.