Patents by Inventor Tadanobu Toba

Tadanobu Toba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11341398
    Abstract: Learning data of a usage environment can be efficiently collected. A recognition apparatus includes: a first neural network configured to receive input of data; a second neural network configured to receive input of the data, the second neural network having a different structure from a structure of the first neural network; a comparison unit configured to compare a first output result of the first neural network and a second output result of the second neural network; and a communication unit configured to wirelessly transmit the data to a host system configured to learn the data when a comparison result between the first output result and the second output result is different by a predetermined standard or more.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: May 24, 2022
    Assignee: HITACHI, LTD.
    Inventors: Tadanobu Toba, Takumi Uezono, Kenichi Shimbo, Goichi Ono
  • Patent number: 11327863
    Abstract: An electronic control device includes: a diagnostic circuit unit configured to be reconfigurable so as to be used to diagnose each of a plurality of processing circuits that processes an input signal; an input data storage unit configured to temporarily store the input signal; an output data storage unit configured to temporarily store an output signal of the plurality of processing circuits; a reconfiguration control unit configured to sequentially write, to the diagnostic circuit unit as circuit configuration information, circuit information the same as that of the plurality of processing circuits; a diagnostic control unit configured to cause the diagnostic circuit unit to perform calculation using the input signal stored in the input data storage unit when the circuit configuration information is written to the diagnostic circuit unit; and a comparator configured to diagnose each of the plurality of processing circuits by comparing output of the diagnostic circuit unit and the output signal stored in the
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: May 10, 2022
    Assignee: Hitachi Astemo, Ltd.
    Inventors: Kenichi Shimbo, Tadanobu Toba, Hideyuki Sakamoto
  • Patent number: 11323344
    Abstract: A data processing method is performed by an edge device acquiring collected data from a collection target and a first computer capable of communicating with the edge device. The method includes: a first calculation process of, by the edge device, storing the collected data in a secure region to which referring of internally stored information from outside is not allowable and calculating first data which has a data amount less than the collected data and is irreversible in the secure region based on the stored collected data; a first communication process of, by the edge device, transmitting the first data calculated through the first calculation process to the first computer; and a second calculation process of, by the first computer, calculating second data based on the first data transmitted from the edge device through the first communication process.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: May 3, 2022
    Assignee: HITACHI, LTD.
    Inventors: Kenichi Shimbo, Tadanobu Toba, Masaharu Kinoshita
  • Publication number: 20220118977
    Abstract: An electronic control unit that is installed on a vehicle connected to a trailer and capable of towing the trailer changes travel control of the vehicle according to a type of the trailer when the trailer is connected to the vehicle.
    Type: Application
    Filed: February 6, 2020
    Publication date: April 21, 2022
    Applicant: Hitachi Astemo, Ltd.
    Inventors: Kenichi SHIMBO, Tadanobu TOBA, Hideyuki SAKAMOTO, Taisuke UETA
  • Publication number: 20220060399
    Abstract: A data processing method is performed by an edge device acquiring collected data from a collection target and a first computer capable of communicating with the edge device. The method includes: a first calculation process of, by the edge device, storing the collected data in a secure region to which referring of internally stored information from outside is not allowable and calculating first data which has a data amount less than the collected data and is irreversible in the secure region based on the stored collected data; a first communication process of, by the edge device, transmitting the first data calculated through the first calculation process to the first computer; and a second calculation process of, by the first computer, calculating second data based on the first data transmitted from the edge device through the first communication process.
    Type: Application
    Filed: June 23, 2021
    Publication date: February 24, 2022
    Applicant: HITACHI, LTD.
    Inventors: Kenichi SHIMBO, Tadanobu TOBA, Masaharu KINOSHITA
  • Patent number: 11247702
    Abstract: Even in a case where an operation abnormality occurs in the arithmetic processing unit of the control device, control is safely shifted to the degeneration control microcomputer, and a vehicle control device capable of improving safety is realized. There are provided an outside world recognition microcomputer 10b, a control microcomputer 11b that outputs a control command to the actuator control device, and a degeneration control microcomputer 12b to which control is shifted in a case where an abnormality occurs in the control microcomputer 11b. The outside world recognition microcomputer 10b calculates a collision potential based on information from the outside world, and determines whether to reset the control microcomputer 11b when an abnormality occurs in the control microcomputer 11b or to shift control to the degeneration control microcomputer 12b.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: February 15, 2022
    Assignee: HITACHI ASTEMO, LTD.
    Inventors: Hideyuki Sakamoto, Tadanobu Toba, Toshiaki Nakamura
  • Publication number: 20220029866
    Abstract: An electronic control unit is mounted on a vehicle, and includes a reception unit that receives a data signal transmitted via a transmission path mounted on the vehicle; an environmental information acquisition unit that acquires environmental information of the vehicle; and a determination unit that determines the state of the transmission path, in which the reception unit includes an equalizer that compensates for the data signal, the equalizer calculates a compensation parameter for compensating for the data signal, and the determination unit determines the state of the transmission path based on the compensation parameter and the environmental information.
    Type: Application
    Filed: February 7, 2020
    Publication date: January 27, 2022
    Applicant: Hitachi Astemo, Ltd.
    Inventors: Tadanobu TOBA, Kenichi SHIMBO, Nozomi KASAHARA, Yutaka UEMATSU, Hideyuki SAKAMOTO
  • Publication number: 20210390795
    Abstract: A distributed system includes an edge device, which is a moving body or equipment capable of automatic operation, and a diagnostic data computer. The edge device includes a moving mechanism or an operating mechanism for automatic operation, and an in-edge controller that controls the moving mechanism or the operating mechanism. Here, the diagnostic data computer: receives diagnostic data indicating an internal state in the in-edge controller.
    Type: Application
    Filed: June 8, 2021
    Publication date: December 16, 2021
    Inventors: Tadanobu TOBA, Takumi UEZONO, Yutaka UEMATSU, Kenichi SHIMBO
  • Publication number: 20210357285
    Abstract: A program for causing a parallel arithmetic device including a plurality of arithmetic groups to execute parallel arithmetic is input. The program includes information defining each of the following: application arithmetic constituting predetermined processing; redundant arithmetic (which is redundant arithmetic of the application arithmetic and is arithmetic assigned to a surplus core(s) in a diagnosis target arithmetic group); and diagnostic arithmetic (arithmetic that is a comparison of results of the same redundant arithmetic by two or more diagnosis target arithmetic groups and is assigned to surplus cores in an arithmetic group for diagnosis). The surplus core(s) is a core(s) to which no application arithmetic is assigned.
    Type: Application
    Filed: May 3, 2021
    Publication date: November 18, 2021
    Inventors: Hiroaki ITSUJI, Takumi UEZONO, Kenichi SHIMBO, Tadanobu TOBA
  • Publication number: 20210318940
    Abstract: An electronic control device includes: a diagnostic circuit unit configured to be reconfigurable so as to be used to diagnose each of a plurality of processing circuits that processes an input signal; an input data storage unit configured to temporarily store the input signal; an output data storage unit configured to temporarily store an output signal of the plurality of processing circuits; a reconfiguration control unit configured to sequentially write, to the diagnostic circuit unit as circuit configuration information, circuit information the same as that of the plurality of processing circuits; a diagnostic control unit configured to cause the diagnostic circuit unit to perform calculation using the input signal stored in the input data storage unit when the circuit configuration information is written to the diagnostic circuit unit; and a comparator configured to diagnose each of the plurality of processing circuits by comparing output of the diagnostic circuit unit and the output signal stored in the
    Type: Application
    Filed: August 7, 2019
    Publication date: October 14, 2021
    Inventors: Kenichi SHIMBO, Tadanobu TOBA, Hideyuki SAKAMOTO
  • Publication number: 20210166422
    Abstract: To detect a discrimination error in a type of an object. A calculation system includes a first device and a second device. The first device includes: a first object map generation unit configured to calculate, using first image information that is image information acquired by the first device, a first object map indicating a type of an object and a position of the object; and a first communication unit configured to transmit the first object map to the second device. The second device includes: a second object map generation unit configured to calculate, using second image information that is image information acquired by the second device, a second object map indicating a type of an object and a position of the object; and a comparison unit configured to compare the first object map and the second object map.
    Type: Application
    Filed: November 24, 2020
    Publication date: June 3, 2021
    Applicant: HITACHI, LTD.
    Inventors: Hiroaki ITSUJI, Takumi UEZONO, Tadanobu TOBA, Kenichi SHIMBO, Yutaka UEMATSU
  • Patent number: 10929273
    Abstract: A verification method for an application logic provided with one or more macro logics configured to perform a predetermined operation, a macro operation control unit configured to instruct the one or more macro logics to start the operation to cause the one or more macro logics to perform the operation, and an operation data storage area configured to store data. In the application logic, static verification by property description of a formal verification language is performed for each of the one or more macro logic, the macro operation control unit, and the operation data storage area, and dynamic verification by simulation is further performed for at least one of the one or more macro logics.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: February 23, 2021
    Assignee: HITACHI, LTD.
    Inventors: Toru Motoya, Masahiro Shiraishi, Satoshi Nishikawa, Keisuke Yamamoto, Tadanobu Toba, Takumi Uezono, Hideo Harada, Yusuke Kanno
  • Publication number: 20200379831
    Abstract: An electronic control device includes a rewritable configuration memory composed of a plurality of frames in which logic circuit information is stored, a reconfiguration control unit configured to rewrite the logic circuit information of the frames, a logic unit configured to form a logic circuit based on the logic circuit information stored in the frames, and a configuration memory diagnosis unit configured to read the logical circuit information stored in the frames of the configuration memory and to perform error detection which is detection of an error in the stored logic circuit information, in which when the frames are rewritten by the reconfiguration control unit, the configuration memory diagnosis unit performs the error detection of ones of the frames that are rewritten prior to ones of the frames that are not rewritten.
    Type: Application
    Filed: November 20, 2018
    Publication date: December 3, 2020
    Inventors: Kenichi SHIMBO, Tadanobu TOBA, Taisuke UETA, Hideyuki SAKAMOTO
  • Publication number: 20200361487
    Abstract: Even in a case where an operation abnormality occurs in the arithmetic processing unit of the control device, control is safely shifted to the degeneration control microcomputer, and a vehicle control device capable of improving safety is realized. There are provided an outside world recognition microcomputer 10b, a control microcomputer 11b that outputs a control command to the actuator control device, and a degeneration control microcomputer 12b to which control is shifted in a case where an abnormality occurs in the control microcomputer 11b. The outside world recognition microcomputer 10b calculates a collision potential based on information from the outside world, and determines whether to reset the control microcomputer 11b when an abnormality occurs in the control microcomputer 11b or to shift control to the degeneration control microcomputer 12b.
    Type: Application
    Filed: December 4, 2018
    Publication date: November 19, 2020
    Applicant: Hitachi Automotive Systems, Ltd.
    Inventors: Hideyuki SAKAMOTO, Tadanobu TOBA, Toshiaki NAKAMURA
  • Publication number: 20200301374
    Abstract: A prediction control device controls an actuator for automatic driving of a vehicle including: a command value generation unit generating an operation amount for the actuator and an operation amount candidate as a predicted value; an output prediction unit outputting a control amount candidate as a predicted value corresponding to the actuator output by using an operation model; an evaluation function calculation unit expressing constraint conditions for the automatic driving; a situation degree detection obtaining a measure of giving priority to ride comfort or giving priority to danger avoidance of an own vehicle while traveling; and a responsiveness adjusting unit obtaining a next operation amount candidate from the situation degree from the situation degree detection unit. The operation command value generation unit generates an operation amount for the actuator, and the responsiveness adjusting unit adjusts the output of the evaluation function according to the situation degree.
    Type: Application
    Filed: September 28, 2018
    Publication date: September 24, 2020
    Applicant: HITACHI AUTOMOTIVE SYSTEMS, LTD.
    Inventors: Toshiaki NAKAMURA, Teppei HIROTSU, Tatsuya HORIGUCHI, Tadanobu TOBA, Hideyuki SAKAMOTO
  • Patent number: 10747920
    Abstract: Provided is a semiconductor LSI design device that includes: a unit that generates a combinational circuit constituted by combining function blocks defined by a function block library from an application specification, by assigning connection information on an operation order of the function blocks; a unit that converts the combinational circuit to operation order information that is applicable to a sequential circuit in which a function block is used a plurality of times in a time-division manner; a unit that inversely converts the generated operation order information to a combinational circuit; a unit that verifies logical equivalence of the combinational circuit and the inversely converted combinational circuit; and a unit that combines the operation order information, the sequential circuit and a function block.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: August 18, 2020
    Assignee: HITACHI, LTD.
    Inventors: Takumi Uezono, Tadanobu Toba, Masahiro Shiraishi, Hideo Harada, Satoshi Nishikawa
  • Publication number: 20200177185
    Abstract: An electronic control device includes: a logic circuit for reconfiguring a plurality of arithmetic circuits including a first circuit and a second circuit; a reconfiguration controller that reconfigures the arithmetic circuits and checks the reconfigured arithmetic circuits based on reconfiguration commands; and a process controller that transmits the reconfiguration commands to the reconfiguration controller and instructs the arithmetic unit to execute operations, in which when a first reconfiguration command is received, the reconfiguration controller reconfigures and checks the first circuit, when the check of the first circuit by the reconfiguration controller is completed, the process controller instructs the first circuit to execute an operation, the process controller transmits a second reconfiguration command to the reconfiguration controller and instructs the reconfiguration controller to start to reconfigure the second circuit until the execution of a predetermined process of the first circuit is co
    Type: Application
    Filed: June 27, 2018
    Publication date: June 4, 2020
    Applicant: HITACHI AUTOMOTIVE SYSTEMS, LTD.
    Inventors: Taisuke UETA, Kenichi SHIMBO, Tadanobu TOBA, Hideyuki SAKAMOTO
  • Publication number: 20190332727
    Abstract: Provided is a semiconductor LSI design device that includes: a unit that generates a combinational circuit constituted by combining function blocks defined by a function block library from an application specification, by assigning connection information on an operation order of the function blocks; a unit that converts the combinational circuit to operation order information that is applicable to a sequential circuit in which a function block is used a plurality of times in a time-division manner; a unit that inversely converts the generated operation order information to a combinational circuit; a unit that verifies logical equivalence of the combinational circuit and the inversely converted combinational circuit; and a unit that combines the operation order information, the sequential circuit and a function block.
    Type: Application
    Filed: April 19, 2019
    Publication date: October 31, 2019
    Applicant: HITACHI, LTD.
    Inventors: Takumi UEZONO, Tadanobu TOBA, Masahiro SHIRAISHI, Hideo HARADA, Satoshi NISHIKAWA
  • Patent number: 10438383
    Abstract: The present invention includes a drawing data generating unit, a variation pattern that varies at regular intervals to be displayed, a display unit that displays drawing data, and a comparator that compares whether input signals are coincident, and the drawing data generating unit includes a receiver that receives data from a higher-level device, a drawing control unit that converts the data received from the higher-level device to drawing data, and a drawing memory that stores the drawing data. The drawing data generating unit and the variation pattern are redundantly configured, and the variation pattern is input to the drawing data generating unit. One output signal of the drawing data generating unit regarding drawing data including the variation pattern is transmitted to the display unit, a plurality of output signals from the drawing data generating unit are input to the comparator, and the comparator outputs a comparison result as a detection signal outside.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: October 8, 2019
    Assignee: HITACHI, LTD.
    Inventors: Tadanobu Toba, Takumi Uezono, Yusuke Kanno, Masahiro Shiraishi, Hideo Harada, Satoru Akasaka
  • Patent number: 10401424
    Abstract: Neutron soft error rate derivation is calculated from data at the low energy neutron radiation. An outline value of an SEU cross-section function corresponding to a given neutron energy value is outputted. This outline value and the low energy neutron spectrum data are used to calculate an error count basic value of errors to occur over time. An error count actual measurement value over time is calculated from an error count during radiation of low energy neutrons and low energy neutron radiation time. The error count basic value and the error count actual measurement are used to calculate a proportionality coefficient of the SEU cross-section function. While holding a natural neutron spectrum, an error rate calculator outputs a neutron flux corresponding to a neutron energy value. The neutron soft error rate is calculated by an integration operation of multiplying the SEU cross-section function with the natural neuron spectrum.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: September 3, 2019
    Assignee: HITACHI, LTD.
    Inventors: Takumi Uezono, Tadanobu Toba, Kenichi Shimbo, Fumihiko Nagasaki