Abstract: A semiconductor inspecting apparatus which is provided with an inspecting unit, a detecting unit, and a processing unit, which processes an image on the basis of reflection light detected by the detecting unit, and which inspects the surface of the subject to be inspected. The processing unit is provided with an image distribution control unit, which distributes the image, and an image processing unit, which processes the image distributed by the image distribution control unit. The image distribution control unit has and image buffer counter, which counts the input image quantity of the image; a distribution control table, which stores information relating to the image; and a distribution timing control circuit, which determines distribution start timing of the image on the basis of the input image quantity and the information relating to the image obtained from the distribution control table.

Abstract: A simulation apparatus includes a discrete events simulation section to perform a discrete type simulation of components of a configured model as defined based on attribute information that is information on parts of the components of the defined configured model and connection information showing a connectional relationship among the components of the defined configured model; and a soft error rate computation processing section to compute a soft error rate of the defined configured model based on the simulation result of the discrete events simulation section and data on soft error rates in the attribute information.

Abstract: When an inspection apparatus of a semiconductor device repeatedly executes computation of prescribed area data, such as image processing for detecting defects, procedures for commanding, data load, computation, and data store need to be repeated the number of times of the computation. This may impose a limitation on the speeding up of the operation. In addition, when performing parallel computation by a high-capacity image processing system for handling minute images, a lot of processors are needed, resulting in an increase in cost.

Abstract: A failure caused by a soft-error including MNU, of an electronic apparatus is prevented, while suppressing increase of a mounting area, power consumption, and processing time. The electronic apparatus stores data indicating the state of a flip-flop included in a sequential logic circuit within an arithmetic unit, each time when execution is performed on a check point provided for every predetermined number of instructions. When a symptom of a soft-error is detected, the apparatus sets the state of the flip-flop included in the sequential logic circuit within the arithmetic unit, based on the data stored after execution of the instruction at the immediately preceding check point, and restarts execution from the next instruction, being subsequent to the instruction associated with the immediately preceding check point.

Abstract: A scan control unit for generating two-dimensional coordinates for performing a scan with an electron beam of an electron scanning microscope is provided with first and second transforming units for transforming coordinates in the horizontal (X) direction and the vertical (V) direction. An area to be tested in a sample is scanned with an electron beam in an arbitrary direction. As the first and second transforming units, small-capacity transformation tables (LUTs) capable of operating at high speed in each of the horizontal (X) direction and the vertical (Y) direction are used. By also using a large-capacity transformation table (LUT) that stores coordinate transformation data corresponding to plural scan types, a test apparatus compatible with the plural scan types, having multiple functions, and capable of performing high-speed scan control is realized.

Abstract: Disclosed is means for quantifying resistance to soft errors in a logic circuit. A logic block group 120 having at least one set comprising a logic block having at least one logic circuit and a sequential circuit that inputs the output of the logic block is arranged in an irradiation region 110 of a high-energy particle irradiation device, and subjected to irradiation with high-energy particles. A control section 101 calculates the error rate of the logic circuit from the value obtained by subtracting the number of errors of the sequential circuit when the logic block of the logic block group 120 is bypassed, from the number of errors of the sequential circuit and the logic block of the logic block group 120.

Abstract: Disclosed is a semiconductor wafer testing apparatus that resolves the following problems which arise when semiconductor wafers become larger: (1) complexity of stage acceleration/deceleration control; (2) throughput reduction; and (3) increased vibration of the stage support platform during the stage inversion operation (deterioration in resolution). In the semiconductor wafer testing apparatus for resolving these problems, a wafer is rotated, an electro beam is irradiated onto the rotating wafer from a scanning electron microscope, and secondary electrons emitted from the wafer are detected. The detected secondary electrons are A/D converted by an image processing unit, realigned by an image data realignment unit, and then image-processed for display. As a result, image information of all dies of a wafer can be acquired without a large amount of movement of the stage in the X and the Y directions.

Abstract: A semiconductor inspecting apparatus includes: a buffer memory whose width is matched to the greater of parallel bus width and the width of the number of serial lanes; a preceding stage bus switching unit that fills the buffer memory with input data without making a free space; equivalent transmission capacity conversion including a following stage bus switching unit that fills read data to the width of an arbitrary number of serial lanes without making a free space; a preceding stage bus switching unit that fills a buffer memory with input data without making a free space; and equivalent transmission capacity inverse conversion including a following stage bus switching unit that fills a parallel bus of arbitrary width with data read from a buffer memory without making a free space.

Abstract: A scan control unit for generating two-dimensional coordinates for performing a scan with an electron beam of an electron scanning microscope is provided with first and second transforming units for transforming coordinates in the horizontal (X) direction and the vertical (V) direction. An area to be tested in a sample is scanned with an electron beam in an arbitrary direction. As the first and second transforming units, small-capacity transformation tables (LUTs) capable of operating at high speed in each of the horizontal (X) direction and the vertical (Y) direction are used. By also using a large-capacity transformation table (LUT) that stores coordinate transformation data corresponding to plural scan types, a test apparatus compatible with the plural scan types, having multiple functions, and capable of performing high-speed scan control is realized.

Abstract: A scan control unit for generating two-dimensional coordinates for performing a scan with an electron beam of an electron scanning microscope is provided with first and second transforming units for transforming coordinates in the horizontal (X) direction and the vertical (V) direction. An area to be tested in a sample is scanned with an electron beam in an arbitrary direction. As the first and second transforming units, small-capacity transformation tables (LUTs) capable of operating at high speed in each of the horizontal (X) direction and the vertical (Y) direction are used. By also using a large-capacity transformation table (LUT) that stores coordinate transformation data corresponding to plural scan types, a test apparatus compatible with the plural scan types, having multiple functions, and capable of performing high-speed scan control is realized.

Abstract: In a circuit board on which a plurality of CPUs are mounted, the CPUs comprises: monitor units for outputting task statuses of the respective CPUs; and a diagnosis circuit connected to the plurality of CPUs, comparing and judging combinations of the task statuses of the plurality of CPUs based on information on task statuses outputted from the monitor units, and detecting false operations and failures of the circuit board.

Abstract: A scan control unit for generating two-dimensional coordinates for performing a scan with an electron beam of an electron scanning microscope is provided with first and second transforming units for transforming coordinates in the horizontal (X) direction and the vertical (V) direction. An area to be tested in a sample is scanned with an electron beam in an arbitrary direction. As the first and second transforming units, small-capacity transformation tables (LUTs) capable of operating at high speed in each of the horizontal (X) direction and the vertical (Y) direction are used. By also using a large-capacity transformation table (LUT) that stores coordinate transformation data corresponding to plural scan types, a test apparatus compatible with the plural scan types, having multiple functions, and capable of performing high-speed scan control is realized.

Abstract: A semiconductor inspecting apparatus includes: a buffer memory whose width is matched to the greater of parallel bus width and the width of the number of serial lanes; a preceding stage bus switching unit that fills the buffer memory with input data without making a free space; equivalent transmission capacity conversion including a following stage bus switching unit that fills read data to the width of an arbitrary number of serial lanes without making a free space; a preceding stage bus switching unit that fills a buffer memory with input data without making a free space; and equivalent transmission capacity inverse conversion including a following stage bus switching unit that fills a parallel bus of arbitrary width with data read from a buffer memory without making a free space.

Abstract: An apparatus diagnosing method is a method in which, in an apparatus including a control apparatus and a control board for controlling the control apparatus, on the controlling board, an error occurrence at the control apparatus and the control board is detected, an error signal is outputted, sensor data outputted from a sensor acquiring data about operation environments of the control apparatus and the control board is collected, and an environmental factor causing a failure or an error of the control apparatus and the control board is specified based upon the error signal and the sensor data, and the sensor data is collected in association with the error signal when the sensor data is collected.

Abstract: In a circuit board on which a plurality of CPUs are mounted, the CPUs comprises: monitor units for outputting task statuses of the respective CPUs; and a diagnosis circuit connected to the plurality of CPUs, comparing and judging combinations of the task statuses of the plurality of CPUs based on information on task statuses outputted from the monitor units, and detecting false operations and failures of the circuit board.

Abstract: When an inspection apparatus of a semiconductor device repeatedly executes computation of prescribed area data, such as image processing for detecting defects, procedures for commanding, data load, computation, and data store need to be repeated the number of times of the computation. This may impose a limitation on the speeding up of the operation. In addition, when performing parallel computation by a high-capacity image processing system for handling minute images, a lot of processors are needed, resulting in an increase in cost.

Abstract: Semiconductor testing equipment according to the present invention comprises: an algorithmic pattern generator for generating a test pattern for testing a memory under test and applying the pattern to the memory under test; a comparator for comparing a response signal from the memory under test and an expected value from tho algorithmic pattern generator; a fail address acquisition part for storing an address of the memory under test (fail address) when a result compared by the comparator is failed; a fail address analysis part for analyzing the failed address and calculating the address to be repaired (repair address); and a cycle-pattern generator for redundancy processing for inserting the address to be repaired into a test pattern and applying the address to the memory under test, so that even when capacity of the semiconductor memory is increased, a fabrication yield thereof is raised by testing the memory after the packaging and by performing the redundancy processing of a defective.

Abstract: A signature circuit, i.e., a random-number generating circuit, is provided in a memory test apparatus. Also, a signature circuit is provided in each of devices-under-test. This configuration allows the large number of semiconductor integrated-circuit devices to be tested at one time with a high efficiency. This condition realizes a tremendous reduction in the test cost.

Abstract: The present invention aims at performing a semiconductor integrated circuit defect analysis with a simplified analysis apparatus and simplifying a defect analysis work. A defect analysis apparatus for a semiconductor integrated circuit is characterized in that a presence/absence of a defect is detected by irradiating an electromagnetic field from a probe to the semiconductor integrated circuit and detecting an electric characteristic variation such as a power supply current variation in the semiconductor integrated circuit.

Abstract: Semiconductor testing equipment according to the present invention comprises: an algorithmic pattern generator for generating a test pattern for testing a memory under test and applying the pattern to the memory under test; a comparator for comparing a response signal from the memory under test and an expected value from tho algorithmic pattern generator; a fail address acquisition part for storing an address of the memory under test (fail address) when a result compared by the comparator is failed; a fail address analysis part for analyzing the failed address and calculating the address to be repaired (repair address); and a cycle-pattern generator for redundancy processing for inserting the address to be repaired into a test pattern and applying the address to the memory under test, so that even when capacity of the semiconductor memory is increased, a fabrication yield thereof is raised by testing the memory after the packaging and by performing the redundancy processing of a defective.