Abstract: An interconnect method in a semiconductor device may include a step of examining various regions of an inter layer dielectric to identify regions having high densities or concentrations of trench features. A cap insulator layer may be added to the dielectric to assist in outgassing of absorbed impurities from the dielectric, but may be removed from the high density areas to allow the lower density areas to increase outgassing. The lower density areas may then compensate for increased outgassing on the high density areas due to the trench features, and may result in an overall device with a more stable dielectric constant across the device.

Abstract: A combustion chamber opening toward a cylinder head is provided on a top surface of a piston, and this combustion chamber comprises a first volume having an inclined surface and a second volume further recessed from the first volume toward a pin boss. Fuel spray F from a fuel injection nozzle is injected toward an inner peripheral wall section of the second volume in a former stage of fuel injection and toward the inclined surface of the first volume in a later stage of fuel injection, and the percentage of the fuel injection period in the former stage against the total fuel injection period is set to the range from 40% to 70%.

Abstract: A combustion chamber (20) opening toward a cylinder head (5) is provided on a top surface (11) of a piston (10), and this combustion chamber (20) comprises a first volume (22) having an inclined surface (20) and a second volume (23) further recessed from the first volume (22) toward a pin boss (13). Fuel spray F from a fuel injection nozzle (9) is injected toward an inner peripheral wall section (24) of the second volume (23) in a former stage of fuel injection and toward the inclined surface (21) of the first volume (22) in a later stage of fuel injection, and the percentage of the fuel injection period in the former stage against the total fuel injection period is set to the range from 40% to 70%.

Abstract: Disclosed is a semiconductor device comprising a substrate, a first region provided on the substrate and comprising a first insulating portion which includes an insulating film having a relative dielectric constant of at most 3.0 and a conductive portion which is provided in the first insulating portion, a second region provided on the substrate, located adjacent to the first region in a direction parallel to a major surface of the substrate and comprising a second insulating portion which is located adjacent to the first insulating portion in the direction and which includes no insulating film having a relative dielectric constant of at most 3.0, and a pad provided on the second region and electrically connected to the conductive portion.

Abstract: A combustion chamber opening toward a cylinder head is provided on a top surface of a piston, and this combustion chamber comprises a first volume having an inclined surface and a second volume further recessed from the first volume toward a pin boss. Fuel spray F from a fuel injection nozzle is injected toward an inner peripheral wall section of the second volume in a former stage of fuel injection and toward the inclined surface of the first volume in a later stage of fuel injection, and the percentage of the fuel injection period in the former stage against the total fuel injection period is set to the range from 40% to 70%.

Abstract: A combustion chamber (20) opening toward a cylinder head (5) is provided on a top surface (11) of a piston (10), and this combustion chamber (20) comprises a first volume (22) having an inclined surface (20) and a second volume (23) further recessed from the first volume (22) toward a pin boss (13). Fuel spray F from a fuel injection nozzle (9) is injected toward an inner peripheral wall section (24) of the second volume (23) in a former stage of fuel injection and toward the inclined surface (21) of the first volume (22) in a later stage of fuel injection, and the percentage of the fuel injection period in the former stage against the total fuel injection period is set to the range from 40% to 70%.

Abstract: Disclosed is a semiconductor device comprising a substrate, a first region provided on the substrate and comprising a first insulating portion which includes an insulating film having a relative dielectric constant of at most 3.0 and a conductive portion which is provided in the first insulating portion, a second region provided on the substrate, located adjacent to the first region in a direction parallel to a major surface of the substrate and comprising a second insulating portion which is located adjacent to the first insulating portion in the direction and which includes no insulating film having a relative dielectric constant of at most 3.0, and a pad provided on the second region and electrically connected to the conductive portion.

Abstract: Disclosed is a semiconductor device comprising a substrate, a first region provided on the substrate and comprising a first insulating portion which includes an insulating film having a relative dielectric constant of at most 3.0 and a conductive portion which is provided in the first insulating portion, a second region provided on the substrate, located adjacent to the first region in a direction parallel to a major surface of the substrate and comprising a second insulating portion which is located adjacent to the first insulating portion in the direction and which includes no insulating film having a relative dielectric constant of at most 3.0, and a pad provided on the second region and electrically connected to the conductive portion.

Abstract: A semiconductor device comprises a semiconductor substrate in which a semiconductor element is formed, an interlayer insulating film formed on the semiconductor substrate, an insulating barrier layer, formed on the interlayer insulating film by plasma nitriding, for preventing diffusion of a metal constituting a wiring layer, a conductive barrier layer, formed on the insulating barrier layer, for preventing diffusion of the metal, and a wiring layer formed of the metal on the conductive barrier layer. A bottom portion of the wiring layer is protected by the conductive barrier layer and the insulating barrier layer. Therefore, the diffusion of the metal constituting the wiring layer can be surely prevented.

Abstract: A metal wiring buried in an insulating layer is subjected to a reducing treatment prior to formation of a second insulating layer on the insulating layer under the condition that the total partial pressure of oxygen and water vapor is sufficiently low.

Abstract: A desired plating film is formed on a surface of a substrate to be treated by performing a film-depositing step based on electroless plating and an etching step alternately and repeatedly. In the film-depositing step, an electroless plating solution is supplied from a nozzle to the surface of the substrate. In the etching step, an etching solution is supplied from a nozzle to the surface of the substrate.

Abstract: Disclosed is a semiconductor device comprising a substrate, a first region provided on the substrate and comprising a first insulating portion which includes an insulating film having a relative dielectric constant of at most 3.0 and a conductive portion which is provided in the first insulating portion, a second region provided on the substrate, located adjacent to the first region in a direction parallel to a major surface of the substrate and comprising a second insulating portion which is located adjacent to the first insulating portion in the direction and which includes no insulating film having a relative dielectric constant of at most 3.0, and a pad provided on the second region and electrically connected to the conductive portion.

Abstract: A semiconductor device comprises a semiconductor substrate in which a semiconductor element is formed, an interlayer insulating film formed on the semiconductor substrate, an insulating barrier layer, formed on the interlayer insulating film by plasma nitriding, for preventing diffusion of a metal constituting a wiring layer, a conductive barrier layer, formed on the insulating barrier layer, for preventing diffusion of the metal, and a wiring layer formed of the metal on the conductive barrier layer. A bottom portion of the wiring layer is protected by the conductive barrier layer and the insulating barrier layer. Therefore, the diffusion of the metal constituting the wiring layer can be surely prevented.

Abstract: A metal wiring buried in an insulating layer is subjected to a reducing treatment prior to formation of a second insulating layer on the insulating layer under the condition that the total partial pressure of oxygen and water vapor is sufficiently low.

Abstract: A semiconductor device manufacturing method comprises a step of forming a trench to a first insulation film formed on a semiconductor substrate, and forming a lower level wiring in the trench, a step of forming at least one conductive layer on the semiconductor substrate to coat the lower level wiring, a step of forming at least one thin film layer on the conductive layer, a step of forming a hard mask by patterning the thin film, a step of etching the conductive layer by using the hard mask as an etching mask, and forming a conductive pillar-shaped structure, whose upper surface is covered with the hard mask, on the lower level wiring, a step of forming a second insulation film on the semiconductor substrate so that the pillar-shaped structure is buried, a step of forming a wiring trench in which at least the hard mask is exposed, and a step of burying a conductor into the wiring trench after the hard mask is removed, and forming an upper level wiring in the wiring trench.

Abstract: A groove or hole is formed in an insulating layer formed on a semiconductor substrate, and a first conductive layer including a first metal element is formed on a surface of the insulating layer. By oxidizing the first conductive layer, an oxide layer of the first metal element is formed on a surface of the first conductive layer. A second conductive layer including a second metal element having a free energy of oxide formation lower than that of the first metal element is deposited thereon. By reducing the oxide layer of the first metal element by the second metal element, an oxide layer of the second metal element is formed at the interface between the first conductive layer and the second conductive layer. Further, an interconnection is buried in the groove or hole of the insulating layer.

Abstract: A piston for internal combustion engines, capable of being manufactured easily and improving the durability of a combustion chamber, moved reciprocatingly in a cylinder of an internal combustion engine, and provided in a top surface thereof with a combustion chamber formed by recessing the same top surface, and in an outer circumferential wall of the combustion chamber with a cooling cavity the inner diameter of a lower portion of an inner circumferential surface of which is set smaller than that of an upper portion thereof, wherein a cross-sectionally angular portion defined by an upper edge portion, at which the combustion chamber is opened in the interior of a cylinder, of an inner circumferential surface of the combustion chamber and a piston-top surface is chamfered greatly in conformity with the cross-sectional shape of the upper portion of the inner circumferential surface of the cooling cavity to such an extent that the thickness of an upper portion of an inner circumferential wall of the cooling cavi

Abstract: A semiconductor device manufacturing method comprises a step of forming a trench to a first insulation film formed on a semiconductor substrate, and forming a lower level wiring in the trench, a step of forming at least one conductive layer on the semiconductor substrate to coat the lower level wiring, a step of forming at least one thin film layer on the conductive layer, a step of forming a hard mask by patterning the thin film, a step of etching the conductive layer by using the hard mask as an etching mask, and forming a conductive pillar-shaped structure, whose upper surface is covered with the hard mask, on the lower level wiring, a step of forming a second insulation film on the semiconductor substrate so that the pillar-shaped structure is buried, a step of forming a wiring trench in which at least the hard mask is exposed, and a step of burying a conductor into the wiring trench after the hard mask is removed, and forming an upper level wiring in the wiring trench.

Abstract: A semiconductor device manufacturing method comprises a step of forming a trench to a first insulation film formed on a semiconductor substrate, and forming a lower level wiring in the trench, a step of forming at least one conductive layer on the semiconductor substrate to coat the lower level wiring, a step of forming at least one thin film layer on the conductive layer, a step of forming a hard mask by patterning the thin film, a step of etching the conductive layer by using the hard mask as an etching mask, and forming a conductive pillar-shaped structure, whose upper surface is covered with the hard mask, on the lower level wiring, a step of forming a second insulation film on the semiconductor substrate so that the pillar-shaped structure is buried, a step of forming a wiring trench in which at least the hard mask is exposed, and a step of burying a conductor into the wiring trench after the hard mask is removed, and forming an upper level wiring in the wiring trench.

Abstract: A method comprises forming a barrier layer for copper metallization, selectively forming a silicon film on a surface of copper wiring formed on the main surface of a semiconductor substrate, and reacting the silicon film with a non-copper metal and/or nitrogen to form a barrier layer in a self-aligned manner relative to the copper wiring. In the method, the capacitance increase in the copper wirings formed is prevented, and the barrier layer formed has a satisfactory barrier property of protecting the copper wirings.