Abstract: A circuit is disclosed which is applied for a digital audio disk (DAD) system for detecting a maximum inverting period of a digital audio signal optically read out from the DAD. The audio signal is prestored in the DAD so as to have the maximum and minimum inverting periods specially set by an eight to fourteen modulation (EFM). The detection circuit includes an edge detector for detecting pulse edges of the digital audio signal, a counter for counting pulse edge intervals on the basis of a modulating clock signal, a counter type register, and a comparator. When the register contents of the counter type register is smaller than the count value of the counter, the comparator produces a pulse signal by which said register updates the contents of the register by "1". Repeating this operation, a maximum inverting period value of the digital audio signal is obtained in a fixed period of time.

Abstract: A data reproduction circuit, which can be used for reproducing audio data from an optical disc, includes a phase-locked loop which has a circuit for detecting polarity inversions of the input signal, a circuit for comparing the phases of a polarity inversion signal with a reference signal, and circuitry for generating an output clock signal which is phase-locked with the input signal, that clock being used to strobe the input signal to remove fluctuation and jitter from the input signal.

Abstract: A data extracting circuit for converting an analog signal derived from a D.C. component-free modulated digital signal stored on a recording medium, into a D.C. component-free digital signal with a comparator for comparing the analog signal with a reference signal to provide a compared signal. A phase inverter receives the compared signal and provides a first signal component which is in-phase with the compared signal, and a second signal component which is phase-inverted with respect to the compared signal. A clipping circuit limits the amplitude level of the first and second signal components to a predetermined level and provides first and second limited signal components. An integrating circuit separately integrates the first and second limited signal components and provides first and second integrated signals. An error amplifying circuit determines the difference between the first and second integrated signals and provides a signal corresponding to this difference to the comparator as the reference signal.

Abstract: The invention relates to a motor control circuit of a data reproduction apparatus, which drives a disk motor to reproduce a data signal recorded together with a sync signal on a recording medium so as to control the disk motor in accordance with a reproduced sync signal. The frequency and phase components of the reproduced sync signal are detected, and first and second motor control signals are produced in accordance with frequency and phase detection signals, respectively. A control circuit detects whether or not the frequency detection signal falls within a predetermined range. If it is determined that the frequency detection signal does not fall within the predetermined range, the second motor control signal is kept at a predetermined value.

Abstract: A wave-shaping circuit which comprises a comparator for comparing the level of a signal reproduced from a magnetic tape on which, for example, PCM signals are recorded with the level of a reference signal, and a D flip-flop circuit for holding an output signal from the comparator for a prescribed period. Where the reproduced signal has a higher level than the original level of the reference signal, then the reference signal is made to have a higher level than the original level by an output signal from the D flip-flop circuit, that is, an output signal from the comparator. Where the reproduced signal has a lower level than the original level of a reference signal, then the reference signal is made to have a lower level than the original level by the output signal from the comparator. As a result, strains occurring at the high density recording are not reproduced.

Abstract: An apparatus divides one element .alpha..sup.i of a Galois field GF(2.sup.m) by another element .alpha..sup.j of the field. Divider data .alpha..sup.j are supplied to one of the first linear shift registers and to the other first linear shift registers through .alpha..sup.N1, .alpha..sup.N2, . . . multiplier circuits, respectively. Simultaneously, dividend data .alpha..sup.i are supplied to one of the second linear shift registers and to the other second linear shift registers through .alpha..sup.N1, .alpha..sup.N2, . . . multiplier circuits, respectively. "1" detector circuits are connected to the outputs of the first linear shift registers, respectively. The first linear shift registers and the second linear shift registers are shifted several times until any "1" detector circuit detects "1" in response to output signals from a 2-input AND gate. When "1" is detected, a NOR gate supplies a signal of logical "0" to the AND gate, whereby the AND gate stops supplying output signals.

Abstract: Data representing one element .alpha..sup.i of a Galois field GF(2.sup.m) are stored in a first linear shift register, and data representing another element .alpha..sup.j of the Galois field GF(2.sup.m) are stored in a second linear shift register. 2.sup.m elements of Galois field GF(2.sup.m) are divided into n groups. A table of the reciprocals of n elements located at specific positions respectively in n groups is stored in a converter which includes a decoder and an encoder. The data representing element .alpha..sup.j are supplied from the second linear shift register to the decoder. If the data representing the reciprocal of element .alpha..sup.j are stored in the converter, they are read from the encoder. If they are not stored in the converter, the first linear shift register and the second linear shift register are shifted N times by control pulses generated by a NOR gate and an AND gate until any one of the reciprocal data are read from the encoder, whereby the register supplies data representing .

Abstract: The invention provides a pulse-width modulation circuit in which an output from a latch circuit for holding a count obtained by counting a reference clock signal in accordance with the period of a signal to be modulated is compared by a comparator with an output from a ramp counter for counting the reference clock signal at a predetermined period so as to perform a pulse-width modulation. The number of bits of the comparator and the ramp counter is decreased by n bits with respect to the number N (N>n) of bits of the latch circuit.

Abstract: An error correcting system uses an error location polynomial which is defined by double correction BCH codes each consisting of the elements of a Galois field GF(2.sup.m), and thereby generates error locations .sigma..sub.1 and .alpha..sup.2 and error patterns e.sub.1 and 2.sub.2. The system has a first data processing system for performing only addition and multiplication to generate the error locations .sigma..sub.1 and .alpha..sup.2, and a second data processing system for performing only addition and multiplication to generate the error patterns e.sub.1 and 2.sub.2. The first data processing system comprises a syndrome generator, a memory, an arithmetic logic unit, registers, latch circuits, registers, adder circuits and a zero detector. The second data processing system comprises a gate circuit, latch circuits, an arithmetic logic unit, and the registers of a memory.

Abstract: A phase locked loop control circuit for a digital audio disk system is disclosed which has a voltage-controlled oscillator (VCO), a reference signal generator for generating a reference signal corresponding to the phase state of a digital audio signal when the digital audio signal is reproduced or read out and which is recorded on a digital audio disk (DAD) to have a maximum or minimum inverting period value predetermined by the eight to fourteen modulation method, a phase comparator connected to the output terminal of the reference signal generator and the VCO, a detector for detecting the maximum inverting period value included in the digital audio signal; and an adder for adding outputs from the phase comparator and the detector and for supplying a sum result as an oscillation control signal to the VCO.

Abstract: A phase sychronizing circuit for a device which reproduces digital data has a phase locked loop including a first phase comparison circuit, a voltage controlled oscillator (VCO) producing an output the frequency of which is controlled by the first phase comparison circuit, and a first frequency divider to divide the output frequency of the VCO. The phase synchronizing circuit further includes second frequency divider for dividing the output frequency of the VCO, a second phase comparison circuit for comparing the phase of a first clock signal from the first frequency divider, with that of a second clock signal from the second frequency divider and a circuit for controlling the frequency dividing ratio of the first frequency dividing circuit according to the phase difference between the first and second clock signals in such a way that the frequency dividing ratio becomes one of 1/N, 1/(N+1) and 1/{(N+(N+1))/2} wherein N is a positive integer.

Abstract: A safety shut-off valve opening a flow path between the primary and secondary sides in case of usual operation, while shutting off the aforesaid path in response to an emergency shut-off signal, and particularly such safety shut-off valve cannot be reset unitl it is confirmed that there is no more leakage of gas on the secondary side of the shut-off valve after the shut-off action was once effected, thereby to attaining a very high safeness.

Abstract: A PCM signal processor for extracting data and error check words from a serial PCM data block contains a serial-to-parallel converter and de-interleaver to present the words in the PCM data block synchronously, circuitry for forming an error pointer and an auxiliary error pointer from the words in the PCM data block error pointer, delay circuitry for forming a data word from the error pointer and the auxiliary error pointer, and error correction and detection circuitry using the data word error pointer.

Abstract: An electromagnetic actuator utilizing a fluid pressure obtained from an electromagnetic pump, wherein according to the present invention, there is provided a responsive member displaceable in response to the pressure of a fluid forced into a second chamber from a first chamber. The responsive member displaceable as described can operate a valve member or the like coupled thereto in an on-off control or a proportional control with a large stroke in a reliable manner.

Abstract: A PCM signal processing apparatus adapted to receive successive transmission blocks, each of which comprise time-interleaved PCM data, error correction and error detection words, and which comprises a detecting circuit responsive to error detecting words for detecting if a received transmission block contains an error, error identifying means for identifying as erroneous each of the time-interleaved words included in the received transmission block which has been detected as containing an error, de-interleaving means for time-deinterleaving each received transmission block to recover a de-interleaved block which comprises de-interleaved PCM and error-correction words.

Abstract: A synchronous circuit comprises a sync signal detecting circuit connected to receive a digital signal with a plurality of frames each consisting of N bits and containing a frame sync signal to detect a sync signal in each frame, and a sync protecting circuit for producing a sync control signal synchronized with the detection of the sync signals and interpolating the sync control signal every frame when the sync signal is not detected. The sync protecting circuit has a counter for counting the number of frames in which the sync signals are not detected. A circuit is provided to quickly synchronize the sync protecting circuit with the detection of the sync signal by the sync signal detecting circuit when noise is produced by the sync signal detecting circuit and then a sync signal is detected after a given value has been counted by the counter.

Abstract: A PCM signal processing apparatus adapted to receive successive transmission blocks, each of which comprise time-interleaved PCM data, error correction and error detection words. The apparatus has detecting means responsive to the error detection words for detecting errors in a received transmission block and error identifying means for identifying errors in each of the time-interleaved words included in the received transmission block which has been detected. A de-interleaver is provided for time-deinterleaving each received transmission block to recover a de-interleaved block comprising de-interleaved PCM and error-correction words, with errors in the de-interleaved words being respectively identified. A syndrome generating device is coupled to the de-interleaver for generating error syndromes using the de-interleaved PCM and error-correction words in the de-interleaved block.

Abstract: A large-aperture single lens with aspherical surfaces to be used as a pickup lens for video disks, especially for tracking the video disk by directly moving the pickup lens. It is preferable that the single lens is made of plastic material in order to make it compact and light in weight. Both refractive surfaces of the single lens are arranged to have positive refractive powers in order to make the working distance of the lens long. Spherical aberration of the single lens is corrected to the degree that the diameter of the circle of confusion thereof is decided approximately by diffraction of light. Both refractive surfaces of the single lens are formed as aspherical surfaces and the shapes of the refractive surfaces are determined so as to correct aberrations including the sine condition to the required range, by taking the error to be caused at the time of manufacture into consideration.

Abstract: A PCM signal processor having a signal input terminal which receives a PCM data signal, a memory for storing the PCM data signal, a standardized signal input terminal for providing a standardized signal corresponding to a synchronizing signal for synchronizing the PCM data signal reproducing apparatus, an address counter for designating the address of the memory which is to be read and means for providing said address counter with preset data in response to the standardized signal.

Abstract: A signal copy device for a digital record/reproduction system includes an encoding circuit for producing a first digital encoded signal corresponding to an analog audio signal. The encoding circuit is connected to a first VTR through a switch section of a switch circuit and a first digital signal processor. A second VTR reproduces and generates a digital encoded audio signal to be copied. The switch circuit is connected to the encoding circuit and the second VTR. The switch circuit includes two switch sections which operate in cooperation with each other. When a reproduction signal is generated from the second VTR, the two switch sections are switched. The reproduction signal is supplied to the first VTR through these switch sections, thus accomplishing copying.