Patents by Inventor Tae-Hong Ha

Tae-Hong Ha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190341302
    Abstract: Apparatuses and methods to provide electronic devices having metal films are provided. Some embodiments of the disclosure utilize a metallic tungsten layer as a liner that is filled with a metal film comprising cobalt. The metallic tungsten layer has good adhesion to the cobalt leading to enhanced cobalt gap-fill performance.
    Type: Application
    Filed: May 2, 2019
    Publication date: November 7, 2019
    Inventors: Yu Lei, Sang-Hyeob Lee, Chris Pabelico, Yi Xu, Tae Hong Ha, Xianmin Tang, Jin Hee Park
  • Publication number: 20190122924
    Abstract: Methods and apparatus for depositing a cobalt layer in a feature, such as, a word line formed in a substrate, are provided herein. In some embodiments, method of processing a substrate includes: exposing a substrate at a first temperature to a cobalt containing precursor to deposit a cobalt layer within a word line feature formed in the substrate, wherein the word line feature is part of a 3D NAND device; and annealing the substrate to remove contaminants from the cobalt layer and to reflow the cobalt layer into the word line feature, wherein the substrate is at a second temperature greater than the first temperature during the annealing.
    Type: Application
    Filed: December 17, 2018
    Publication date: April 25, 2019
    Inventors: JIN HEE PARK, TAE HONG HA, SANG-HYEOB LEE, THOMAS JONGWAN KWON, JAESOO AHN, XIANMIN TANG, ER-XUAN PING, SREE KESAPRAGADA
  • Publication number: 20190115254
    Abstract: Methods and apparatus to fill a feature with a seamless gapfill of copper are described. A copper gapfill seed layer is deposited on a substrate surface by atomic layer deposition followed by a copper deposition by physical vapor deposition to fill the gap with copper.
    Type: Application
    Filed: October 12, 2018
    Publication date: April 18, 2019
    Inventors: Ben-Li Sheu, Feng Q. Liu, Tae Hong Ha, Mei Chang, Shirish Pethe
  • Patent number: 10157787
    Abstract: Methods and apparatus for depositing a cobalt layer in a feature, such as, a word line formed in a substrate, are provided herein. In some embodiments, method of processing a substrate includes: exposing a substrate at a first temperature to a cobalt containing precursor to deposit a cobalt layer within a word line feature formed in the substrate, wherein the word line feature is part of a 3D NAND device; and annealing the substrate to remove contaminants from the cobalt layer and to reflow the cobalt layer into the word line feature, wherein the substrate is at a second temperature greater than the first temperature during the annealing.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: December 18, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Jin Hee Park, Tae Hong Ha, Sang-Hyeob Lee, Thomas Jongwan Kwon, Jaesoo Ahn, Xianmin Tang, Er-Xuan Ping, Sree Kesapragada
  • Publication number: 20180297666
    Abstract: Provided is a bicycle with an automatic transmission, and more particularly, a bicycle with an automatic transmission for enabling rapid and smooth gearshifting from a low speed to a high speed or from a high speed to a low speed.
    Type: Application
    Filed: April 5, 2018
    Publication date: October 18, 2018
    Inventors: Min Soo HA, Jinsu HA, Tae Hong HA
  • Patent number: 10014179
    Abstract: Methods for processing a substrate include: (a) depositing a cobalt layer to a first thickness within a first plurality of features and a second plurality of features formed in a substrate, wherein each of the first plurality of features and each of the second plurality of features comprises an opening, and wherein a width of the openings of the first plurality of features is less than a width of the openings of the second plurality of features; and (b) heating the substrate to a first temperature to fill the first plurality of features with cobalt material while simultaneously depositing a fill material on the substrate to fill the second plurality of features.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: July 3, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Rong Tao, Tae Hong Ha, Xianmin Tang, Joung Joo Lee
  • Patent number: 10002834
    Abstract: A method and apparatus for forming an interconnect on a substrate is provided. A protective layer is formed on the substrate and in a via formed on the substrate wherein the protective layer is resistant to a halogen containing material. A barrier layer is formed on top of the protective layer. The barrier layer comprises a halogen containing material. A metal layer is deposited over the barrier layer. In another embodiment, the protective layer is selectively deposited in the via.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: June 19, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Mehul B. Naik, Paul F. Ma, Tae Hong Ha, Srinivas Guggilla
  • Patent number: 9938622
    Abstract: Methods for depositing ruthenium by a PECVD process are described herein. Methods for depositing ruthenium can include positioning a substrate in a processing chamber, the substrate having a barrier layer formed thereon, heating and maintaining the substrate at a first temperature, flowing a first deposition gas into a processing chamber, the first deposition gas comprising a ruthenium containing precursor, generating a plasma from the first deposition gas to deposit a first ruthenium layer over the barrier layer, flowing a second deposition gas into the processing chamber to deposit a second ruthenium layer over the first ruthenium layer, the second deposition gas comprising a ruthenium containing precursor, depositing a copper seed layer over the second ruthenium layer and annealing the substrate at a second temperature.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: April 10, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Tae Hong Ha, Sang Ho Yu, Kiejin Park
  • Publication number: 20170178956
    Abstract: Methods and apparatus for depositing a cobalt layer in a feature, such as, a word line formed in a substrate, are provided herein. In some embodiments, method of processing a substrate includes: exposing a substrate at a first temperature to a cobalt containing precursor to deposit a cobalt layer within a word line feature formed in the substrate, wherein the word line feature is part of a 3D NAND device; and annealing the substrate to remove contaminants from the cobalt layer and to reflow the cobalt layer into the word line feature, wherein the substrate is at a second temperature greater than the first temperature during the annealing.
    Type: Application
    Filed: December 19, 2016
    Publication date: June 22, 2017
    Inventors: Jin Hee PARK, Tae Hong HA, Sang-Hyeob LEE, Thomas Jongwan KWON, Jaesoo AHN, Xianmin TANG, Er-Xuan PING, Sree KESAPRAGADA
  • Patent number: 9677172
    Abstract: Methods for forming a liner layer are provided herein. In some embodiments, a method of forming a liner layer on a substrate disposed in a process chamber, the substrate having an opening formed in a first surface of the substrate, the opening having a sidewall and a bottom surface, the method includes exposing the substrate to a cobalt precursor gas and to a ruthenium precursor gas to form a cobalt-ruthenium liner layer on the first surface of the substrate and on the sidewall and bottom surface of the opening.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: June 13, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Tae Hong Ha, Wei Lei, Kie Jin Park
  • Publication number: 20160268207
    Abstract: A method and apparatus for forming an interconnect on a substrate is provided. A protective layer is formed on the substrate and in a via formed on the substrate wherein the protective layer is resistant to a halogen containing material. A barrier layer is formed on top of the protective layer. The barrier layer comprises a halogen containing material. A metal layer is deposited over the barrier layer. In another embodiment, the protective layer is selectively deposited in the via.
    Type: Application
    Filed: May 13, 2015
    Publication date: September 15, 2016
    Inventors: Mehul B. NAIK, Paul F. MA, Tae Hong HA, Srinivas GUGGILLA
  • Publication number: 20160240432
    Abstract: Methods for processing a substrate include: (a) depositing a cobalt layer to a first thickness within a first plurality of features and a second plurality of features formed in a substrate, wherein each of the first plurality of features and each of the second plurality of features comprises an opening, and wherein a width of the openings of the first plurality of features is less than a width of the openings of the second plurality of features; and (b) heating the substrate to a first temperature to fill the first plurality of features with cobalt material while simultaneously depositing a fill material on the substrate to fill the second plurality of features.
    Type: Application
    Filed: February 9, 2016
    Publication date: August 18, 2016
    Inventors: RONG TAO, TAE HONG HA, XIANMIN TANG, JOUNG JOO LEE
  • Publication number: 20160160350
    Abstract: Methods for depositing ruthenium by a PECVD process are described herein. Methods for depositing ruthenium can include positioning a substrate in a processing chamber, the substrate having a barrier layer formed thereon, heating and maintaining the substrate at a first temperature, flowing a first deposition gas into a processing chamber, the first deposition gas comprising a ruthenium containing precursor, generating a plasma from the first deposition gas to deposit a first ruthenium layer over the barrier layer, flowing a second deposition gas into the processing chamber to deposit a second ruthenium layer over the first ruthenium layer, the second deposition gas comprising a ruthenium containing precursor, depositing a copper seed layer over the second ruthenium layer and annealing the substrate at a second temperature.
    Type: Application
    Filed: February 17, 2016
    Publication date: June 9, 2016
    Inventors: Tae Hong HA, Sang Ho YU, Kiejin PARK
  • Publication number: 20150203961
    Abstract: Methods for forming a liner layer are provided herein. In some embodiments, a method of forming a liner layer on a substrate disposed in a process chamber, the substrate having an opening formed in a first surface of the substrate, the opening having a sidewall and a bottom surface, the method includes exposing the substrate to a cobalt precursor gas and to a ruthenium precursor gas to form a cobalt-ruthenium liner layer on the first surface of the substrate and on the sidewall and bottom surface of the opening.
    Type: Application
    Filed: January 21, 2015
    Publication date: July 23, 2015
    Inventors: TAE HONG HA, Wei Lei, Kie Jin Park
  • Publication number: 20140134351
    Abstract: Methods for depositing ruthenium by a PECVD process are described herein. Methods for depositing ruthenium can include positioning a substrate in a processing chamber, the substrate having a barrier layer formed thereon, heating and maintaining the substrate at a first temperature, flowing a first deposition gas into a processing chamber, the first deposition gas comprising a ruthenium containing precursor, generating a plasma from the first deposition gas to deposit a first ruthenium layer over the barrier layer, flowing a second deposition gas into the processing chamber to deposit a second ruthenium layer over the first ruthenium layer, the second deposition gas comprising a ruthenium containing precursor, depositing a copper seed layer over the second ruthenium layer and annealing the substrate at a second temperature.
    Type: Application
    Filed: August 15, 2013
    Publication date: May 15, 2014
    Applicant: Applied Materials, Inc.
    Inventors: Tae Hong Ha, Sang Ho Yu, Kiejin Park
  • Patent number: 8476162
    Abstract: Methods for forming layers on a substrate are provided herein. In some embodiments, methods of forming layers on a substrate disposed in a process chamber may include depositing a barrier layer comprising titanium within one or more features in the substrate; and sputtering a material from a target in the presence of a plasma formed from a process gas by applying a DC power to the target, maintaining a pressure of less than about 500 mTorr within the process chamber, and providing up to about 5000 W of a substrate bias RF power to deposit a seed layer comprising the material atop the barrier layer.
    Type: Grant
    Filed: October 7, 2011
    Date of Patent: July 2, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Tae Hong Ha, Winsor Lam, Tza-Jing Gung, Joung Joo Lee
  • Publication number: 20120108058
    Abstract: Methods for forming layers on a substrate are provided herein. In some embodiments, methods of forming layers on a substrate disposed in a process chamber may include depositing a barrier layer comprising titanium within one or more features in the substrate; and sputtering a material from a target in the presence of a plasma formed from a process gas by applying a DC power to the target, maintaining a pressure of less than about 500 mTorr within the process chamber, and providing up to about 5000 W of a substrate bias RF power to deposit a seed layer comprising the material atop the barrier layer.
    Type: Application
    Filed: October 7, 2011
    Publication date: May 3, 2012
    Applicant: APPLIED MATERIALS, INC.
    Inventors: TAE HONG HA, WINSOR LAM, TZA-JING GUNG, JOUNG JOO LEE
  • Publication number: 20110315319
    Abstract: Apparatus for processing substrates are disclosed herein. In some embodiments, a substrate processing system may include a process chamber having a first volume to receive a plasma and a second volume for processing a substrate; a substrate support disposed in the second volume; and a plasma filter disposed in the process chamber between the first volume and the second volume such that a plasma formed in the first volume can only flow from the first volume to the second volume through the plasma filter. In some embodiments, the substrate processing system includes a process kit coupled to the process chamber, wherein the plasma filter is disposed in the process kit.
    Type: Application
    Filed: June 22, 2011
    Publication date: December 29, 2011
    Applicant: APPLIED MATERIALS, INC.
    Inventors: JOHN C. FORSTER, TAE HONG HA, MURALI K. NARASIMHAN, XINYU FU, ARVIND SUNDARRAJAN, XIAOXI GUO
  • Patent number: 8043922
    Abstract: A method of fabricating a semiconductor device, can be provided by forming gate structures for transistors on a semiconductor substrate in a cell region and in a peripheral circuit region. An offset spacer can be formed including a first material on the gate structures. A first ion implantation can be done using the gate structures and the offset spacer as an ion implantation mask to form source/drain regions. A material layer can be formed including a second material on the semiconductor substrate and on the gate structures. A material layer can be formed of a third material, having an etch selectivity with respect to the second material, on the material layer of the second material. An etch-back can be performed the material layer comprising the third material in the cell region and in the peripheral region, to simultaneously expose the source/drains region in the peripheral region and not expose the source/drain regions in the cell region.
    Type: Grant
    Filed: January 29, 2010
    Date of Patent: October 25, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-bum Lee, Tae-hong Ha, Seong-hwee Cheong
  • Publication number: 20100197103
    Abstract: A method of fabricating a semiconductor device can include forming gate structures for transistors on a semiconductor substrate in a cell region and in a peripheral circuit region, forming an offset spacer of a first material on the gate structure, performing first ion implantation for source/drain region formation using the gate structures and the offset spacer as an ion implantation mask, forming a material layer of a second material on the semiconductor substrate and the gate structures, forming a material layer of a third material, which has an etch selectivity with respect to the second material, on the material layer made of the second material, etching-back the material layer made of the third material using the material layer made of the second material as an etch stop layer to form a multi-layered spacer comprising the second material and the third material, performing second ion implantation for source/drain region formation using the gate structures and the multi-layered spacer as an ion implantati
    Type: Application
    Filed: January 29, 2010
    Publication date: August 5, 2010
    Inventors: Jun-bum Lee, Tae-hong Ha, Seong-hwee Cheong