Patents by Inventor TaeWoo Kang
TaeWoo Kang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11967308Abstract: Disclosed is an electronic device including processor and memory operatively connected to the processor and storing language model. The electronic device may enter data into the language model, generate an embedding vector in the input embedding layer, add position information to the embedding vector in the positional encoding layer, branch the embedding vector based on domain information, normalize the branched embedding vectors, enter the normalized embedding vectors into the multi-head attention layer, enter output data of the multi-head attention layer into the first layer, normalize pieces of output data of the first layer, enter the normalized pieces of output data of the first layer into the feed-forward layer, enter output data of the feed-forward layer into the second layer and normalize pieces of output data of the second layer, and enter the normalized pieces of output data of the second layer into the linearization layer and the softmax layer to obtain result data.Type: GrantFiled: July 8, 2021Date of Patent: April 23, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Taewoo Lee, Taegyoon Kang, Hogyeong Kim, Minjoong Lee, Seokyeong Jung, Jiseung Jeong
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Patent number: 11715697Abstract: A semiconductor package may include a lower package including a first substrate, a first semiconductor chip on the first substrate, and a first molding portion on the first substrate to cover the first semiconductor chip, an interposer substrate on the first semiconductor chip, a supporting portion between the interposer substrate and the first substrate to support the interposer substrate, a connection terminal connecting the interposer substrate to the first substrate, and an upper package on the interposer substrate. The upper package may include a second substrate, a second semiconductor chip on the second substrate, and a second molding portion on the second substrate to cover the second semiconductor chip.Type: GrantFiled: November 12, 2020Date of Patent: August 1, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Sungbum Kim, Taewoo Kang, Jaewon Choi
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Publication number: 20230144388Abstract: A semiconductor package includes a package substrate including a first chip mounting area, a second chip mounting area, and a third chip mounting area spaced apart from one another in a first direction, semiconductor chips mounted on the first to third chip mounting areas, a first stiffener mounted on the package substrate to separate the first chip mounting area from the second chip mounting area, and a second stiffener mounted on the package substrate to separate the second chip mounting area from the third chip mounting area.Type: ApplicationFiled: November 8, 2022Publication date: May 11, 2023Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Heungkyu KWON, Taewoo Kang, Taehun Kim
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Publication number: 20210183780Abstract: A semiconductor package may include a lower package including a first substrate, a first semiconductor chip on the first substrate, and a first molding portion on the first substrate to cover the first semiconductor chip, an interposer substrate on the first semiconductor chip, a supporting portion between the interposer substrate and the first substrate to support the interposer substrate, a connection terminal connecting the interposer substrate to the first substrate, and an upper package on the interposer substrate. The upper package may include a second substrate, a second semiconductor chip on the second substrate, and a second molding portion on the second substrate to cover the second semiconductor chip.Type: ApplicationFiled: November 12, 2020Publication date: June 17, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Sungbum KIM, Taewoo KANG, Jaewon CHOI
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Patent number: 10651074Abstract: A substrate processing apparatus may include a substrate jig device and a transfer unit, which is configured to hold a substrate in a non-contact state and move the substrate toward the substrate jig device. The substrate jig device may include a supporter, which is configured to support an edge of the substrate and have an opening, a first suction part, which overlaps with a center region of the opening and is configured to move in a first direction, and a plurality of second suction parts, which overlap with an edge region of the opening and are configured to move toward the opening. Here, the first direction may be a direction passing through the opening.Type: GrantFiled: May 16, 2017Date of Patent: May 12, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyoung Hwan Kim, Taewoo Kang, Byung Lyul Park, Hyungjun Jeon
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Publication number: 20180114714Abstract: A substrate processing apparatus may include a substrate jig device and a transfer unit, which is configured to hold a substrate in a non-contact state and move the substrate toward the substrate jig device. The substrate jig device may include a supporter, which is configured to support an edge of the substrate and have an opening, a first suction part, which overlaps with a center region of the opening and is configured to move in a first direction, and a plurality of second suction parts, which overlap with an edge region of the opening and are configured to move toward the opening. Here, the first direction may be a direction passing through the opening.Type: ApplicationFiled: May 16, 2017Publication date: April 26, 2018Inventors: KYOUNG HWAN KIM, TAEWOO KANG, Byung Lyul PARK, HYUNGJUN JEON
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Patent number: 9922897Abstract: A method of manufacturing a semiconductor package includes forming a preliminary package, on a supporting substrate, which includes a connection substrate, a semiconductor chip and a molding pattern on the connection substrate and the semiconductor chip, forming a buffer pattern on the molding pattern, and forming a carrier substrate, on the buffer pattern, which includes a first portion contacting the buffer pattern and a second portion contacting the molding pattern.Type: GrantFiled: April 6, 2017Date of Patent: March 20, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyoung Hwan Kim, Taewoo Kang, Byung Lyul Park, Hyungjun Jeon
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Publication number: 20180076108Abstract: A method of manufacturing a semiconductor package includes forming a preliminary package, on a supporting substrate, which includes a connection substrate, a semiconductor chip and a molding pattern on the connection substrate and the semiconductor chip, forming a buffer pattern on the molding pattern, and forming a carrier substrate, on the buffer pattern, which includes a first portion contacting the buffer pattern and a second portion contacting the molding pattern.Type: ApplicationFiled: April 6, 2017Publication date: March 15, 2018Inventors: Kyoung Hwan KIM, Taewoo KANG, Byung Lyul PARK, Hyungjun JEON
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Patent number: 9773685Abstract: A flip chip interconnect has a tapering interconnect structure, and the area of contact of the interconnect structure with the site on the substrate metallization is less than the area of contact of the interconnect structure with the die pad. A solder mask has an opening over the interconnect site, and the solder mask makes contact with the interconnect structure at the margin of the opening. The flip chip interconnect is provided with an underfill. During the underfill process, the contact or near proximity of the solder mask with the interconnect structure interferes with flow of the underfill material toward the substrate adjacent the site, resulting in formation of a void left unfilled by the underfill, adjacent the contact of the interconnect structure with the site on the substrate metallization. The void can help provide relief from strain induced by changes in temperature of the system.Type: GrantFiled: June 21, 2012Date of Patent: September 26, 2017Assignee: STATS ChipPAC Pte. Ltd.Inventors: Rajendra D. Pendse, KyungOe Kim, TaeWoo Kang
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Patent number: 9373573Abstract: A flip chip interconnect has a tapering interconnect structure, and the area of contact of the interconnect structure with the site on the substrate metallization is less than the area of contact of the interconnect structure with the die pad. Also, a bond-on-lead or bond-on-narrow pad or bond on a small area of a contact pad interconnection includes such tapering flip chip interconnects. Also, methods for making the interconnect structure include providing a die having interconnect pads, providing a substrate having interconnect sites on a patterned conductive layer, providing a bump on a die pad, providing a fusible electrically conductive material either at the interconnect site or on the bump, mating the bump to the interconnect site, and heating to melt the fusible material.Type: GrantFiled: June 16, 2014Date of Patent: June 21, 2016Assignee: STATS ChipPAC Pte. Ltd.Inventors: Rajendra D. Pendse, KyungOe Kim, TaeWoo Kang
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Patent number: 8901734Abstract: An interconnect pad is formed over a first substrate. A photoresist layer is formed over the first substrate and interconnect pad. A portion of the photoresist layer is removed to form a channel and expose a perimeter of the interconnect pad while leaving the photoresist layer covering a central area of the interconnect pad. A first conductive material is deposited in the channel of the photoresist layer to form a column of conductive material. The remainder of the photoresist layer is removed. A masking layer is formed around the column of conductive material while exposing the interconnect pad within the column of conductive material. A second conductive material is deposited over the first conductive layer. The second conductive material extends above the column of conductive material. The masking layer is removed. The second conductive material is reflowed to form a column interconnect structure over the semiconductor device.Type: GrantFiled: April 3, 2012Date of Patent: December 2, 2014Assignee: STATS ChipPAC, Ltd.Inventors: SungWon Cho, TaeWoo Kang
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Publication number: 20140291839Abstract: A flip chip interconnect has a tapering interconnect structure, and the area of contact of the interconnect structure with the site on the substrate metallization is less than the area of contact of the interconnect structure with the die pad. Also, a bond-on-lead or bond-on-narrow pad or bond on a small area of a contact pad interconnection includes such tapering flip chip interconnects. Also, methods for making the interconnect structure include providing a die having interconnect pads, providing a substrate having interconnect sites on a patterned conductive layer, providing a bump on a die pad, providing a fusible electrically conductive material either at the interconnect site or on the bump, mating the bump to the interconnect site, and heating to melt the fusible material.Type: ApplicationFiled: June 16, 2014Publication date: October 2, 2014Inventors: Rajendra D. Pendse, KyungOe Kim, TaeWoo Kang
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Patent number: 8810029Abstract: A flip chip interconnect has a tapering interconnect structure, and the area of contact of the interconnect structure with the site on the substrate metallization is less than the area of contact of the interconnect structure with the die pad. Also, a bond-on-lead or bond-on-narrow pad or bond on a small area of a contact pad interconnection includes such tapering flip chip interconnects. Also, methods for making the interconnect structure include providing a die having interconnect pads, providing a substrate having interconnect sites on a patterned conductive layer, providing a bump on a die pad, providing a fusible electrically conductive material either at the interconnect site or on the bump, mating the bump to the interconnect site, and heating to melt the fusible material.Type: GrantFiled: February 6, 2012Date of Patent: August 19, 2014Assignee: STATS ChipPAC, Ltd.Inventors: Rajendra D. Pendse, KyungOe Kim, TaeWoo Kang
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Patent number: 8779570Abstract: A stackable integrated circuit package system including mounting an integrated circuit device over a package carrier, mounting a stiffener over the package carrier and mounting a mountable package carrier over the stiffener with a vertical gap between the integrated circuit device and the mountable package carrier.Type: GrantFiled: March 19, 2008Date of Patent: July 15, 2014Assignee: STATS ChipPAC Ltd.Inventors: Seong Bo Shim, TaeWoo Kang, Yong Hee Kang
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Patent number: 8703541Abstract: An electronic system is provided including forming a substrate having a radiating patterned pad, mounting an electrical device having an external interconnect over the radiating patterned pad with the external interconnect offset from the radiating patterned pad, and aligning the external interconnect with the radiating patterned pad.Type: GrantFiled: April 6, 2012Date of Patent: April 22, 2014Assignee: Stats Chippac Ltd.Inventors: Haengcheol Choi, Ki Youn Jang, Taewoo Kang, Il Kwon Shim
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Publication number: 20140061890Abstract: A semiconductor package may include a semiconductor chip mounted on a substrate, a molding part protecting the semiconductor chip and having a top surface at a substantially equal height to a top surface of the semiconductor chip, a heat exhausting part on the molding part and the semiconductor chip, and an adhesive part between the heat exhausting part and the molding part and between the heat exhausting part and the semiconductor chip. An interface between the heat exhausting part and the adhesive part has a concave-convex structure.Type: ApplicationFiled: August 29, 2013Publication date: March 6, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: Jung-Do Lee, Taewoo Kang, Donghan Kim, JongBo Shim, Yang-hoon Ahn, SeokWon Lee, Dae-young Choi
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Publication number: 20120273943Abstract: A flip chip interconnect has a tapering interconnect structure, and the area of contact of the interconnect structure with the site on the substrate metallization is less than the area of contact of the interconnect structure with the die pad. A solder mask has an opening over the interconnect site, and the solder mask makes contact with the interconnect structure at the margin of the opening. The flip chip interconnect is provided with an underfill. During the underfill process, the contact or near proximity of the solder mask with the interconnect structure interferes with flow of the underfill material toward the substrate adjacent the site, resulting in formation of a void left unfilled by the underfill, adjacent the contact of the interconnect structure with the site on the substrate metallization. The void can help provide relief from strain induced by changes in temperature of the system.Type: ApplicationFiled: June 21, 2012Publication date: November 1, 2012Applicant: STATS CHIPPAC, LTD.Inventors: Rajendra D. Pendse, KyungOe Kim, TaeWoo Kang
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Patent number: RE44562Abstract: A flip chip interconnect has a tapering interconnect structure, and the area of contact of the interconnect structure with the site on the substrate metallization is less than the area of contact of the interconnect structure with the die pad. A solder mask has an opening over the interconnect site, and the solder mask makes contact with the interconnect structure, or is in close proximity to the interconnect structure, at the margin of the opening. The flip chip interconnect is provided with an underfill. During the underfill process, the contact (or near proximity) of the solder mask with the interconnect structure interferes with flow of the underfill material toward the substrate adjacent the site, resulting in formation of a void left unfilled by the underfill, adjacent the contact of the interconnect structure with the site on the substrate metallization. The void can help provide relief from strain induced by changes in temperature of the system.Type: GrantFiled: July 26, 2012Date of Patent: October 29, 2013Assignee: STATS ChipPAC, Ltd.Inventors: Rajendra D. Pendse, KyungOe Kim, TaeWoo Kang
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Patent number: RE44608Abstract: A flip chip interconnect has a tapering interconnect structure, and the area of contact of the interconnect structure with the site on the substrate metallization is less than the area of contact of the interconnect structure with the die pad. Also, a bond-on-lead or bond-on-narrow pad or bond on a small area of a contact pad interconnection includes such tapering flip chip interconnects. Also, methods for making the interconnect structure include providing a die having interconnect pads, providing a substrate having interconnect sites on a patterned conductive layer, providing a bump on a die pad, providing a fusible electrically conductive material either at the interconnect site or on the bump, mating the bump to the interconnect site, and heating to melt the fusible material.Type: GrantFiled: February 1, 2013Date of Patent: November 26, 2013Assignee: STATS ChipPAC, Ltd.Inventors: Rajendra D. Pendse, KyungOe Kim, TaeWoo Kang
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Patent number: RE44761Abstract: A flip chip interconnect has a tapering interconnect structure, and the area of contact of the interconnect structure with the site on the substrate metallization is less than the area of contact of the interconnect structure with the die pad. A solder mask has an opening over the interconnect site, and the solder mask makes contact with the interconnect structure, or is in close proximity to the interconnect structure, at the margin of the opening. The flip chip interconnect is provided with an underfill. During the underfill process, the contact (or near proximity) of the solder mask with the interconnect structure interferes with flow of the underfill material toward the substrate adjacent the site, resulting in formation of a void left unfilled by the underfill, adjacent the contact of the interconnect structure with the site on the substrate metallization. The void can help provide relief from strain induced by changes in temperature of the system.Type: GrantFiled: February 1, 2013Date of Patent: February 11, 2014Assignee: STATS ChipPAC, Ltd.Inventors: Rajendra D. Pendse, KyungOe Kim, TaeWoo Kang