Abstract: A method and apparatus for laterally urging two semiconductor chips, dies or wafers into an improved state of registration with each other, the method and apparatus employing microstructures comprising: a first microstructure disposed on a first major surface of a first one of said two semiconductor chips, dies or wafers, wherein the first microstructure includes a sidewall which is tapered thereby disposing it at an acute angle compared to a perpendicular of said first major surface, and a second microstructure disposed on a first surface of a second one of said two semiconductor chips, dies or wafers, wherein the shape of the second microstructure is complementary to, and mates with or contacts, in use, the first microstructure, the second microstructure including a surface which contacts said sidewall when the first and second microstructures are mated or being mated, the sidewall of the first microstructure and the surface of the second microstructure imparting a lateral force for urging the two semicondu

Abstract: A semiconductor power handling device, includes a cathode pillar, a gate surrounding the cathode pillar, and an anode spaced from the cathode by a nano-vacuum gap. An array of semiconductor power handling devices, each comprising a cathode pillar, a gate surrounding the cathode pillar, and an anode spaced from the cathode pillar by a nano-vacuum gap. The semiconductor power handling devices can be arranged as rows and columns and can be interconnected to meet the requirements of various applications. The array of power handling devices can be fabricated on a single substrate.

Abstract: A neuroelectric sensor and stimulator system includes a first antenna, a reader coupled to the first antenna for transmitting stimulation controls and power to a second antenna, and for receiving sensor data transmitted from the second antenna via the first antenna, and at least one neuroelectric sensor stimulator array including the second antenna, a rectifier coupled to the second antenna for extracting power transmitted from the first antenna, a controller coupled to the second antenna for decoding controls transmitted from the first antenna to the second antenna for the neuroelectric sensor stimulator array, a plurality of sensors, a multiplexer coupled to the controller and to the plurality of sensors for selecting a single sensor, and a plurality of stimulators coupled to the controller for stimulating neurons, wherein the rectifier, the controller, the plurality of sensors, the multiplexer, and the plurality of stimulators include graphene.

Abstract: A compound semiconductor integrated circuit comprising a first substrate; a first electronic component formed on top of said first substrate; a layer of a first dielectric material formed on top of said first substrate and including said first electronic component, said layer of a first dielectric material comprising a recess exposing a first region of said first substrate; and a layer of a second dielectric material attached to said first substrate on top of said first region of said first substrate after manufacturing of said layer of a second dielectric material, said layer of a second material comprising a second electronic component.

Abstract: A neuroelectric sensor and stimulator system includes a first antenna, a reader coupled to the first antenna for transmitting stimulation controls and power to a second antenna, and for receiving sensor data transmitted from the second antenna via the first antenna, and at least one neuroelectric sensor stimulator array including the second antenna, a rectifier coupled to the second antenna for extracting power transmitted from the first antenna, a controller coupled to the second antenna for decoding controls transmitted from the first antenna to the second antenna for the neuroelectric sensor stimulator array, a plurality of sensors, a multiplexer coupled to the controller and to the plurality of sensors for selecting a single sensor, and a plurality of stimulators coupled to the controller for stimulating neurons, wherein the rectifier, the controller, the plurality of sensors, the multiplexer, and the plurality of stimulators include graphene.

Abstract: Polymeric and co-polymeric compositions useful for preparing ophthalmic and ocular devices, such as implantable intraocular lenses (IOL) and contact lenses, and processes of forming the compositions and devices are provided. The disclosed polymeric or co-polymeric composition may include a curcuminoid compound as a UV-blocker, and is derived from a pre-polymerization mixture of monomers which comprises at least 50 weight percents acrylate monomers and exhibiting visible light transparency and ultraviolet light opacity. The disclosed co-polymeric composition may alternatively, or in addition, be derived from a pre-polymerization mixture of defined monomers.

Abstract: The disclosed antenna structures and electronic microsystems are capable of physically disappearing in a controlled, triggerable manner. Some variations provide an on-chip transient antenna comprising a semiconductor substrate containing ion-implanted hydrogen atoms and a conductor network comprising metals bridged by low-melting-temperature metals. Some variations provide an off-chip transient antenna comprising a flexible substrate containing a polymer, nanoporous silicon particles, and an oxidant for silicon, and a conductor network comprising metals bridged by low-melting-temperature metals. Other variations provide a method of introducing physical transience to a semiconductor integrated circuit, comprising thinning a substrate from the back side, implanting hydrogen ions into the thinned substrate to introduce latent structural flaws, depositing a semiconductor integrated circuit or sensor chip, and providing a controllable heating source capable of activating the latent structural flaws.

Abstract: A compound semiconductor integrated circuit comprising a first substrate; a first electronic component formed on top of said first substrate; a layer of a first dielectric material formed on top of said first substrate and including said first electronic component, said layer of a first dielectric material comprising a recess exposing a first region of said first substrate; and a layer of a second dielectric material attached to said first substrate on top of said first region of said first substrate after manufacturing of said layer of a second dielectric material, said layer of a second material comprising a second electronic component.

Abstract: A semiconductor power handling device, includes a cathode pillar, a gate surrounding the cathode pillar, and an anode spaced from the cathode by a nano-vacuum gap. An array of semiconductor power handling devices, each comprising a cathode pillar, a gate surrounding the cathode pillar, and an anode spaced from the cathode pillar by a nano-vacuum gap. The semiconductor power handling devices can be arranged as rows and columns and can be interconnected to meet the requirements of various applications. The array of power handling devices can be fabricated on a single substrate.

Abstract: A method for fabricating a digital memristor crossbar array includes applying a protective layer on at least a portion of a memristive layer. A method for fabricating an analog memristor crossbar array includes providing a self-aligning first electrode layer. An analog memristor includes a memristive layer bar arranged to self-align said second electrode on said memristive layer along its length.

Abstract: A field effect transistor (FET) having a source, a drain and a gate includes a first connection electrically connected to the gate near a first end of the gate, a second connection electrically connected to the gate near the first end of the gate, a third connection electrically connected to the gate near a second end of the gate, and a fourth connection electrically connected to the gate near the second end of the gate. By performing gate resistance measurements at different ambient temperatures, a thermal coefficient of gate resistance can be derived and then used to monitor the gate temperature, which is representative of the channel temperature.

Abstract: A multifocal lens device is disclosed. The device comprises a lens body being formed with a plurality of concentric annular zones separated by slanted steps. The concentric zones effect both diffraction and refraction of incident light, while the steps are substantially devoid of any diffractive or refractive power.

Abstract: A multifocal ophthalmic device is disclosed, wherein the lens body comprises a curcuminoid compound as a UV-light stabilizer, and/or a co-polymeric composition which is derived from a pre-polymerization mixture of defined monomers. The lens body of the multifocal ophthalmic device is being formed with a plurality of concentric annular zones, which effect both diffraction and refraction of incident light, and which are separated by slanted steps that are substantially devoid of any diffractive or refractive power.

Abstract: A method of fabricating a normally “off” GaN heterostructure field effect transistor having a source and a drain including depositing a passivation layer patterned to cover a channel region between a source and a drain, forming a first opening in the passivation layer, the first opening for defining a gate area in the channel region and the first opening having a first length dimension along a direction of current flow between the source and the drain, and implanting ions in an implant area within the gate area, wherein the implant area has a second length dimension along the direction of current flow shorter than the first length dimension.

Abstract: A method of three dimensional heterogeneous integration including forming HBT devices on a first substrate, each HBT device having a collector, removing the first substrate, forming first bonding pads on each collector of the heterojunction bipolar transistor devices, forming high electron mobility transistor (HEMT) devices on a first side of a growth substrate, wherein the growth substrate comprises a thermally conductive substrate, such as SiC or diamond, forming second bonding pads on the first side of the growth substrate, aligning and bonding the first bonding pads to the second bonding pads, forming CMOS devices on a Si substrate, bonding the CMOS devices on the Si substrate to a second side of the growth substrate, and forming selectively interconnects between the HBT devices, the HEMT devices, and the CMOS devices by forming vias and first and second level metal interconnects.

Abstract: A heterojunction bipolar transistor (HBT) having an emitter, a base, and a collector, the base including a first semiconductor layer coupled to the collector, the first semiconductor layer having a first bandgap between a first conduction band and a first valence band and a second semiconductor layer coupled to the first semiconductor layer and having a second bandgap between a second conduction band and a second valence band, wherein the second valence band is higher than the first valence band and wherein the second semiconductor layer comprises a two dimensional hole gas and a third semiconductor layer coupled to the second semiconductor layer and having a third bandgap between a third conduction band and a third valence band, wherein the third valence band is lower than the second valence band and wherein the third semiconductor layer is coupled to the emitter.

Abstract: A cartridge for implantation of a deformable intraocular lens (IOL) through a small incision in the eye, including a body portion including a first section including a first lens delivery passageway configured to contain an IOL readied for implantation, and a second section including a second lens delivery passageway connected to the first passageway, configured to fold the IOL when the IOL is pushed through the second passageway, and a nozzle portion extending from the body portion, the nozzle portion including a third passageway and a tip for insertion through the incision in the eye, the second passageway extending to the third passageway, the third passageway configured to transfer the folded IOL into an incision in an eye when the folded IOL is pushed through the nozzle. Related apparatus and methods are also described.

Abstract: The present invention, in some embodiments thereof, provides a method and device for automatically calculating, prior to an IOL (intraocular lens) implantation procedure in a patient, a power and an axis location of the IOL in the implantation procedure, the method comprising: inputting to an electronic device keratometry parameters of the patient; inputting to the electronic device surgical parameters of the IOL implantation procedure on the patient; analyzing the patient keratometry parameters and the surgical parameters by the electronic device; and automatically determining by the electronic device the power and the axis location of the IOL in the implantation procedure in response to the inputs.

Abstract: A method of fabricating a normally “off” GaN heterostructure field effect transistor having a source and a drain including depositing a passivation layer patterned to cover a channel region between a source and a drain, forming a first opening in the passivation layer, the first opening for defining a gate area in the channel region and the first opening having a first length dimension along a direction of current flow between the source and the drain, and implanting ions in an implant area within the gate area, wherein the implant area has a second length dimension along the direction of current flow shorter than the first length dimension.

Abstract: A field effect transistor (FET) having a source, a drain and a gate includes a first connection electrically connected to the gate near a first end of the gate, a second connection electrically connected to the gate near the first end of the gate, a third connection electrically connected to the gate near a second end of the gate, and a fourth connection electrically connected to the gate near the second end of the gate. By performing gate resistance measurements at different ambient temperatures, a thermal coefficient of gate resistance can be derived and then used to monitor the gate temperature, which is representative of the channel temperature.