Abstract: A combinationally doped semiconductor layer, a double heterojunction bipolar transistor (DHBT) including a combinationally doped semiconductor layer, and a method of making a combinationally doped semiconductor layer employ a combination of carbon and beryllium doping. The combinationally doped semiconductor layer includes a first sublayer of a semiconductor material doped substantially with beryllium and a second sublayer of the semiconductor material doped substantially with carbon. The DHBT includes a carbon-beryllium combinationally doped semiconductor layer as a base layer. The method of making a combinationally doped semiconductor layer includes growing a first sublayer of the semiconductor layer, the first sublayer being doped substantially with beryllium and growing a second sublayer of the semiconductor layer, the second sublayer being doped substantially with carbon.

Abstract: A method for fabricating heterojunction bipolar transistors that exhibit simultaneous low base resistance and short base transit times, which translate into semiconductor devices with low power consumption and fast switching times, is presented. The method comprises acts for fabricating a set of extrinsic layers by depositing a highly-doped p+ layer on a substrate, depositing a masking layer on highly-doped p+ layer, patterning the masking layer with a masking opening, removing a portion of the highly-doped p+ layer and the substrate through the masking opening in the masking layer to form a well, and growing an intrinsic layered device in the well by a combination of insitu etching and epitaxial regrowth, where an intrinsic layer has a thickness selected independently from a thickness of its corresponding extrinsic layer, thus allowing the resulting device to have thick extrinsic base layer (low base resistance) and thin intrinsic base layer (short base transit times) simultaneously.

Abstract: A multifocal ophthalmic device is disclosed, wherein the lens body comprises a curcuminoid compound as a UV-light stabilizer, and/or a co-polymeric composition which is derived from a pre-polymerization mixture of defined monomers The lens body of the multifocal ophthalmic device is being formed with a plurality of concentric annular zones, which effect both diffraction and refraction of incident light, and which are separated by slanted steps that are substantially devoid of any diffractive or refractive power.

Abstract: Polymeric and co-polymeric compositions useful for preparing ophthalmic and ocular devices, such as implantable intraocular lenses (IOL) and contact lenses, and processes of forming the compositions and devices are provided. The disclosed polymeric or co-polymeric composition may include a curcuminoid compound as a UV-blocker, and is derived from a pre-polymerization mixture of monomers which comprises at least 50 weight percents acrylate monomers and exhibiting visible light transparency and ultraviolet light opacity. The disclosed co-polymeric composition may alternatively, or in addition, be derived from a pre-polymerization mixture of defined monomers.

Abstract: A multifocal lens device is disclosed. The device comprises a lens body being formed with a plurality of concentric annular zones separated by slanted steps. The concentric zones effect both diffraction and refraction of incident light, while the steps are substantially devoid of any diffractive or refractive power.

Abstract: A heterojunction bipolar transistor (HBT) having an emitter, a base, and a collector, the base including a first semiconductor layer coupled to the collector, the first semiconductor layer having a first bandgap between a first conduction band and a first valence band and a second semiconductor layer coupled to the first semiconductor layer and having a second bandgap between a second conduction band and a second valence band, wherein the second valence band is higher than the first valence band and wherein the second semiconductor layer comprises a two dimensional hole gas and a third semiconductor layer coupled to the second semiconductor layer and having a third bandgap between a third conduction band and a third valence band, wherein the third valence band is lower than the second valence band and wherein the third semiconductor layer is coupled to the emitter.

Abstract: A method for fabricating a semiconductor device which protects the ohmic metal contacts and the channel of the device during subsequent high temperature processing steps is explained. An encapsulation layer is used to cover the channel and ohmic metal contacts. The present invention provides a substrate on which a plurality of semiconductor layers are deposited. The semiconductor layers act as the channel of the device. The semiconductor layers are covered with an encapsulation layer. A portion of the encapsulation layer and the plurality of semiconductor layers are removed, wherein ohmic metal contacts are deposited. The ohmic metal contacts are then annealed to help reduce their resistance. The encapsulation layer ensures that the ohmic metal contacts do not migrate during the annealing step and that the channel is not harmed by the high temperatures needed during the annealing step.

Abstract: A bipolar junction transistor having an emitter, a base, and a collector includes a stack of one or more layer sets adjacent the collector. Each layer set includes a first material having a first band gap, wherein the first material is highly doped, and a second material having a second band gap narrower than the first band gap, wherein the second material is at most lightly doped.

Abstract: A method for fabricating a semiconductor device which protects the ohmic metal contacts and the channel of the device during subsequent high temperature processing steps is explained. An encapsulation layer is used to cover the channel and ohmic metal contacts. The present invention provides a substrate on which a plurality of semiconductor layers are deposited. The semiconductor layers act as the channel of the device. The semiconductor layers are covered with an encapsulation layer. A portion of the encapsulation layer and the plurality of semiconductor layers are removed, wherein ohmic metal contacts are deposited. The ohmic metal contacts are then annealed to help reduce their resistance. The encapsulation layer ensures that the ohmic metal contacts do not migrate during the annealing step and that the channel is not harmed by the high temperatures needed during the annealing step.

Abstract: A method for fabricating heterojunction field effect transistors (HFET) and a family of HFET layer structures are presented. In the method, a step of depositing a HFET semiconductor structure onto a substrate is performed. Next, a photoresist material is deposited. Portions of the photoresist material are removed corresponding to source and drain pad pairs. A metal layer is deposited onto the structure, forming source pad and drain pad pairs. The photoresist material is removed, exposing the structure in areas other than the source and drain pad pairs. Each source and drain pad pair has a corresponding exposed area. The structure is annealed and devices are electrically isolated. The exposed area of each device is etched to form a gate recess and a gate structure is formed in the recess. Semiconductor layer structures for GaN/AlGaN HFETs are also presented.

Abstract: Bipolar junction transistors (BJTs) and single or double heterojunction bipolar transistors with low parasitics, and methods for making the same is presented. A transistor is fabricated such that the collector region underneath a base contact area is deactivated. This results in a drastic reduction of the base-collector parasitic capacitance, Cbc. An embodiment of the present invention provides a transistor architecture for which the base contact area can be decoupled from the collector and hence allows for dramatic reduction in the parasitics of transistors.

Abstract: A method for fabricating a semiconductor device which protects the ohmic metal contacts and the channel of the device during subsequent high temperature processing steps is explained. An encapsulation layer is used to cover the channel and ohmic metal contacts. The present invention provides a substrate on which a plurality of semiconductor layers are deposited. The semiconductor layers act as the channel of the device. The semiconductor layers are covered with an encapsulation layer. A portion of the encapsulation layer and the plurality of semiconductor layers are removed, wherein ohmic metal contacts are deposited. The ohmic metal contacts are then annealed to help reduce their resistance. The encapsulation layer ensures that the ohmic metal contacts do not migrate during the annealing step and that the channel is not harmed by the high temperatures needed during the annealing step.

Abstract: A method for fabricating heterojunction bipolar transistors that exhibit simultaneous low base resistance and short base transit times, which translate into semiconductor devices with low power consumption and fast switching times, is presented. The method comprises acts for fabricating a set of extrinsic layers by depositing a highly-doped p+ layer on a substrate, depositing a masking layer on highly-doped p+ layer, patterning the masking layer with a masking opening, removing a portion of the highly-doped p+ layer and the substrate through the masking opening in the masking layer to form a well, and growing an intrinsic layered device in the well by a combination of insitu etching and epitaxial regrowth, where an intrinsic layer has a thickness selected independently from a thickness of its corresponding extrinsic layer, thus allowing the resulting device to have thick extrinsic base layer (low base resistance) and thin intrinsic base layer (short base transit times) simultaneously.

Abstract: A method for fabricating heterojunction field effect transistors (HFET) and a family of HFET layer structures are presented. In the method, a step of depositing a HFET semiconductor structure onto a substrate is performed. Next, a photoresist material is deposited. Portions of the photoresist material are removed corresponding to source and drain pad pairs. A metal layer is deposited onto the structure, forming source pad and drain pad pairs. The photoresist material is removed, exposing the structure in areas other than the source and drain pad pairs. Each source and drain pad pair has a corresponding exposed area. The structure is annealed and devices are electrically isolated. The exposed area of each device is etched to form a gate recess and a gate structure is formed in the recess. Semiconductor layer structures for GaN/AlGaN HFETs are also presented.

Abstract: Bipolar junction transistors (BJTs) and single or double heterojunction bipolar transistors with low parasitics, and methods for making the same is presented. A transistor is fabricated such that the collector region underneath a base contact area is deactivated. This results in a drastic reduction of the base-collector parasitic capacitance, Cbc. An embodiment of the present invention provides a transistor architecture for which the base contact area can be decoupled from the collector and hence allows for dramatic reduction in the parasitics of transistors.

Abstract: A method and apparatus for depositing self-aligned base contacts where over-etching the emitter sidewall to undercut the emitter contact is not needed. A semiconductor structure has a T-shaped emitter contact that comprises a T-top and T-foot. The T-top acts as a mask for depositing the base contacts. In forming the T-top, its dimensions may be varied, thereby allowing the spacing between the base contacts and emitter to be adjusted.

Abstract: A system and method for facilitating information interexchange between a wireless telecommunications system having at least one telecommunications device therein and an information service provider. A Business-to-Business (B2B) engine is connected to the telecommunications system for receiving realtime information related to a telecommunications device within the telecommunications system. This realtime information is provided by the B2B engine to the information service provider, which consequently provides content data to the telecommunications device within the telecommunications system.

Abstract: The present invention provides a GaN based DHFET that helps confine the 2DEG to the channel layer, and reduces the 2DHG. The present invention provides a GaN DHFET having a channel layer comprising GaN and a buffer layer comprising AlxGa1?xN. The Al content in the buffer layer is specifically chosen based on the thickness of the channel layer using a graph. By choosing the Al content in the buffer layer and thickness of the channel layer in accordance with the graph provided in the present invention, the ability of the buffer layer to help confine the 2DEG to the channel layer is improved.

Abstract: A system, method, and apparatus for facilitating information interexchange between a telecommunications network serving a wireless communications device and an information service provider. A Business-to-Business (B2B) engine polls a telecommunications node associated with the telecommunications network serving the wireless communications device for real-time information. The telecommunications node responds by transmitting the requested real-time information to the B2B engine, which, in turn, provides the received real-time information to the information service provider. The information service provider, in turn, provides a service, tailored according to the real-time information received, to a subscriber associated with the wireless communications device.

Abstract: A method for fabricating a semiconductor device which protects the ohmic metal contacts and the channel of the device during subsequent high temperature processing steps is explained. An encapsulation layer is used to cover the channel and ohmic metal contacts. The present invention provides a substrate on which a plurality of semiconductor layers are deposited. The semiconductor layers act as the channel of the device. The semiconductor layers are covered with an encapsulation layer. A portion of the encapsulation layer and the plurality of semiconductor layers are removed, wherein ohmic metal contacts are deposited. The ohmic metal contacts are then annealed to help reduce their resistance. The encapsulation layer ensures that the ohmic metal contacts do not migrate during the annealing step and that the channel is not harmed by the high temperatures needed during the annealing step.