Abstract: A method and apparatus are provided to prevent or reduce stiction of a MEMS device. The MEMS device may include a protrusion extending from a surface of the MEMS device. During manufacture, the protrusion may be connected across an opening in the MEMS device to a sidewall of the substrate. Before manufacture of the MEMS device is completed, at least a portion of the protrusion connecting the MEMS device to the substrate may be removed. During operation, the protrusion may provide stiction prevention or reduction for the surface from which the first protrusion may extend. A plurality of protrusions may be formed along a plurality of surfaces for the MEMS device to prevent or reduce stiction along the corresponding surfaces. Protrusions may also be formed on devices surrounding or encapsulating the MEMS device to prevent or reduce stiction of the MEMS device to the surrounding or encapsulating devices.

Abstract: A junction gate field-effect transistor (JFET) includes a substrate, a source region formed in the substrate, a drain region formed in the substrate, a channel region formed in the substrate, and at least one gate region formed in the substrate. The channel region connects the source and drain regions. The at least one gate region is configured to cause a depletion region in one of the source and drain regions.

Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); an upper low-k (LK) dielectric layer over the lower ESL; a first conductive feature in the upper LK dielectric layer, wherein the first conductive feature has a first metal line and a dummy via contiguous with the first metal line, the dummy via extending through the lower ESL; a first gap along an interface of the first conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the first conductive feature, and the first gap.

Abstract: A semiconductor structure comprises a metal gate structure formed in a substrate, wherein the metal gate structure comprises a first film formed of a first material and formed on a bottom and sidewalls of a gate trench, a second film formed of a second material and formed over the first film and a gate electrode formed over the second film. The semiconductor structure further comprises a resistor structure formed in the substrate, where the resistor structure comprises a third film formed of the first material and formed on a bottom and sidewalls of a resistor trench and a fourth film formed of the second material and formed over the third film.

Abstract: A semiconductor circuit includes an array of repeating blocks, each of the blocks having a device, and at least one signal line connecting the devices of the blocks. A model of the semiconductor circuit is generated to include a functional area corresponding to at least one first block of the array, and a loading area corresponding to at least one second block of the array. In the functional area, parasitic parameters of the at least one signal line and the device of the at least one first block are extracted. In the loading area, parasitic parameters of the at least one signal line are extracted, but parasitic parameters of the device of the at least one second block are not extracted.

Abstract: An embodiment is a semiconductor device comprising an optical device over a first substrate, a vertical waveguide on a top surface of the optical device, the vertical waveguide having a first refractive index, and a capping layer over the vertical waveguide, the capping layer configured to be a lens for the vertical waveguide and the capping layer having a second refractive index.

Abstract: An integrated semiconductor device for manipulating and processing bio-entity samples and methods are described. The device includes a lower substrate, at least one optical signal conduit disposed on the lower substrate, at least one cap bonding pad disposed on the lower substrate, a cap configured to form a capped area, and disposed on the at least one cap bonding pad, a microfluidic channel, wherein a first side of the microfluidic channel is formed on the lower substrate and a second side of the microfluidic channel is formed on the cap, a photosensor array coupled to sensor control circuitry, and logic circuitry coupled to the fluidic control circuitry, and the sensor control circuitry.

Abstract: In a timing delay characterization method, a signal path between an input terminal and an output terminal of a semiconductor circuit is divided into an input stage, a processing stage, and an output stage. An operation of the input stage is simulated at various input parameter values of an input parameter at the input terminal to obtain corresponding extrinsic input timing delays associated with the input stage. An operation of the processing stage is simulated to obtain an intrinsic timing delay associated with the processing stage. An operation of the output stage is simulated at various output parameter values of an output parameter at the output terminal to obtain corresponding extrinsic output timing delays associated with the output stage. A timing delay data store is generated or populated based on the extrinsic input timing delays, the extrinsic output timing delays and the intrinsic timing delay.

Abstract: The present disclosure provides a resistive random access memory (RRAM) cells and methods of making the same. The RRAM cell includes a transistor and an RRAM structure. The RRAM structure includes a bottom electrode having a via portion and a non-planar portion, a resistive material layer conformally covering the non-planar portion of the bottom electrode; and, a top electrode on the resistive material layer. The via portion of the bottom electrode is embedded in a first RRAM stop layer. The non-planar portion of the bottom electrode has an apex and is centered above the via portion.

Abstract: Presented herein is a method for electrolessly forming a metal cap in a via opening, comprising bringing a via into contact with metal solution, the via disposed in an opening in a substrate, and forming a metal cap in the opening and in contact with the via, the metal cap formed by an electroless chemical reaction. A metal solution may be applied to the via to form the metal cap. The metal solution may comprises at least cobalt and the cap may comprise at least cobalt, and may optionally further comprise tungsten, and wherein the forming the cap comprises forming the cap to further comprise at least tungsten. The metal solution may further comprise at least hypophosphite or dimethlyaminoborane.

Abstract: Defect-describing (or “cut”) layer(s) for describing defects associated with different sides of a 3-dimensional (3D) structure enable fault modeling to determine the effect of position and location of defects on transistor performance. One or more defect-describing layers are used to identify the coordinates and sides of the 3D structures of the defects. The defect-describing layer(s) enables fault-modeling for 3D structures to understand the effects of faults on different locations, especially for defects associated with the fins of the finFET devices. Faults are injected to different locations and sides of fins and are modeled with different test vectors, test parameters and testing devices to identify detectable faults. The fault modeling would help identify the sources of defects and also improve layout design of finFET device structures.

Abstract: Disclosed are a wafer carrier that keeps wafers under a constant pressure, at any preset value below or above the atmospheric pressure, to prevent wafer contaminations arising from atmospheric exposure in conventional wafer carriers, and also, a wafer transport system and method utilizing the same wafer carrier. The wafer carrier charged with a preset carrier pressure is transported and docked with an airlock of a wafer processing tool comprising the airlock, a vacuum transfer module, and a process chamber. The airlock adjusts, by a gas pump, inner pressure to equate successively with, first, the carrier pressure before opening the carrier door, and next, the vacuum transfer module pressure before opening the latter's door. The wafers are then transferred into the process chamber. After processing, the wafers are transferred back into the wafer carrier and charged with the preset carrier pressure before undocked and transported to the next wafer processing tool.

Abstract: A system and method for photoresists is provided. In an embodiment a cross-linking or coupling reagent is included within a photoresist composition. The cross-linking or coupling reagent will react with the polymer resin within the photoresist composition to cross-link or couple the polymers together, resulting in a polymer with a larger molecular weight. This larger molecular weight will cause the dissolution rate of the photoresist to decrease, leading to a better depth of focus for the line.

Abstract: A varainductor including a signal line disposed over a substrate. The varainductor further includes a first ground plane over the substrate, the first ground plane disposed on a first side of the signal line, and a second ground plane over the substrate, the second ground plane disposed on a second side of the signal line opposite the first side of the signal line. The varainductor further includes a first floating plane over the substrate, the first floating plane disposed between the first ground plane and the signal line, and a second floating plane over the substrate, the second floating plane disposed between the second ground plane and the signal line. The varainductor further includes an array of switches, the array of switches is configured to selectively connect the first ground plane to the first floating plane, and to selectively connect the second ground plane to the second floating plane.

Abstract: A testing holder for a chip unit, a multi site holding frame for plural chip units and a method for testing a die thereof are provided. The proposed multi site holding frame for testing plural chip units simultaneously includes a first holder frame having a plurality of testing holders. Each of the plurality of testing holders includes a holder body containing a specific one of the plural chip units, and a pressure releasing device formed on the holder body to release an insertion pressure when the specific one of the plural chip units is inserted in the holder body.

Abstract: Disclosed herein is a method of forming a coating, comprising applying a first coating to a substrate having a plurality of topographical features, planarizing a top surface of the first coating, and drying the coating after planarizing the top surface of the first coating. The first coating may be applied over the plurality of topographical features, and substantially liquid during application. The first coating may optionally be a conformal coating over topographical features of the substrate. The conformal coating may be dried prior to planarizing the top surface of the first coating and a solvent applied to the conformal coating, with the top surface of the conformal coating being substantially planar after application of the solvent. The coating may have a planar surface prior to the drying the first coating and the first coating may be dried without substantial spin-drying by modifying an environment of the first coating.

Abstract: An integrated circuit device incorporating a plurality of isolation trench structures configured for disparate applications and a method of forming the integrated circuit are disclosed. In an exemplary embodiment, a substrate having a first region and a second region is received. A first isolation trench is formed in the first region, and a second isolation trench is formed in the second region. A first liner layer is formed in the first isolation trench, and a second liner layer is formed in the second isolation trench. The second liner layer has a physical characteristic that is different from a corresponding physical characteristic of the first liner layer. An implantation procedure is performed on the second isolation trench and the second liner layer formed therein. The physical characteristic of the second liner layer may be selected to enhance an implantation depth or an implantation uniformity compared to the first liner layer.

Abstract: A system and method for treating a filter is provided. In an embodiment the filter is treated by pre-rinsing the filter membrane with a buffer solvent. The buffer solvent can be used to reduce or eliminate energy differences between the surface of the filter membrane and the process liquid which is being filtered. The pre-rinse may be performed prior to shipment or, alternatively, may be performed after shipment of the filter to a customer.

Abstract: A metal plating apparatus includes a chemical bath chamber, an anode disposed at a bottom portion of the chemical bath chamber, and a cathode disposed at a top portion of the chemical bath chamber. A solenoid coil is disposed within the chemical bath chamber between the anode and the cathode. The solenoid coil is arranged to apply a magnetic field during a metal plating process in a direction from the anode to the cathode.

Abstract: Disclosed herein is a method of forming a stress relieved film stack, the method comprising forming a film stack on a first side of a substrate, the film stack comprising a plurality of film layers and creating a plurality of film stack openings according to a cutting pattern and along at least a portion of a buffer region. The plurality of film stack openings extend from a top surface of the film stack to the substrate. A deflection of the substrate may be determined, and the cutting pattern selected prior to creating the film stack openings based on the deflection of the substrate. The substrate may have a deflection of less than about 2 ?m after the creating the plurality of film stack openings. And at least one of the plurality of film layers may comprise one of titanium nitride, silicon carbide and silicon dioxide.