Abstract: A method of designing a charge trapping memory array including designing a floating gate memory array layout. The floating gate memory layout includes a first type of transistors, electrical connections between memory cells of the floating gate memory array layout, a first input/output (I/O) interface, a first type of charge pump, and an I/O block. The method further includes modifying the floating gate memory array layout, using a processor, to replace the first type of transistors with a second type of transistors different than the first type of transistors. The method further includes determining an operating voltage difference between the I/O block and the second type of transistors. The method further includes modifying the floating gate memory array layout, using the processor, to modify the first charge pump based on the determined operating voltage difference.

Abstract: Packages for semiconductor devices, packaged semiconductor devices, and methods of cooling packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes a substrate including a semiconductor device mounting region, a cover coupled to a perimeter of the substrate, and members disposed between the substrate and the cover. The package includes partitions, with each partition being disposed between two adjacent members. The package includes a fluid inlet port coupled to the cover, and a fluid outlet port coupled to one of the partitions.

Abstract: A method includes coating a photo resist over an Under-Bump Metallurgy (UBM) layer and exposing the photo resist. In the step of exposing, a light amount reaching a bottom of the photo resist is less than about 5 percent of a light amount reaching a top surface of the photo resist. The method further includes developing the photo resist to form an opening in the photo resist. A portion of the UBM layer is exposed through the opening. The opening has a bottom lateral dimension greater than a top lateral dimension. An electrical connector is formed in the opening, wherein the electrical connector is non-reflowable.

Abstract: Methods and apparatus are disclosed for manufacturing metal contacts under ground-up contact pads within a device. A device may comprise a bottom metal layer with a bottom metal contact, a top metal layer with a top metal contact, and a plurality of middle metal layers. Any given metal layer of the plurality of middle metal layers comprises a metal contact, the metal contact is substantially vertically below the top metal contact, substantially vertically above the bottom metal contact, and substantially vertically above a metal contact in any metal layer that is below the given metal layer. The metal contacts may be of various and different shapes. All the metal contacts in the plurality of middle metal layers and the bottom metal contact may be smaller than the top metal contact, therefore occupying less area and saving more area for other functions such as device routing.

Abstract: Embodiments of the present disclosure are a semiconductor device, a FinFET device, and a method of forming a FinFET device. An embodiment is a semiconductor device comprising a first semiconductor fin extending above a substrate, a first source region on the first semiconductor fin, and a first drain region on the first semiconductor fin. The first source region has a first width and the first drain region has a second width with the second width being different than the first width.

Abstract: A method includes coining solder balls of a bottom package, wherein top surfaces of the solder balls are flattened after the step of coining. The solder balls are molded in a molding material. The top surfaces of the solder balls are through trenches in the molding material.

Abstract: A method of forming a nitrogen-containing oxide film is disclosed. The method comprises (a) exposing a substrate to a first gas pulse having one of an oxygen-containing gas and a metal-containing gas; (b) exposing the substrate to a second gas pulse having the other of the oxygen-containing gas and the metal-containing gas to form an oxide film over the substrate; and (c) exposing the oxide film to a third gas pulse having a nitrogen-containing plasma to form a nitrogen-containing oxide film, wherein the nitrogen-containing oxide film has a nitrogen concentration between about 0.1 and about 3 atomic percent (at %).

Abstract: An embodiment radio frequency area of an integrated circuit includes a substrate having a first resistance, the substrate including an implant region, a buried oxide layer disposed over the substrate, an interface layer between the substrate and the buried oxide layer, the interface layer having a second resistance lower than the first resistance, a silicon layer disposed over the buried oxide layer, and an interlevel dielectric disposed in a deep trench, the deep trench extending through the silicon layer, the buried oxide layer, and the interface layer over the implant region. In an embodiment, the deep trench extends through a polysilicon layer disposed over the silicon layer.

Abstract: The invention relates to an isolation structure of a semiconductor device. An exemplary isolation structure for a semiconductor device comprises a substrate comprising a trench; a strained material in the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; an oxide layer of the strained material over the strained material; a high-k dielectric layer over the oxide layer; and a dielectric layer over the high-k dielectric layer filling the trench.

Abstract: Lithography mask repair methods are disclosed. In one embodiment, a method of repairing a lithography mask includes providing a lithography mask, exposing a back side of the lithography mask to vacuum ultraviolet (VUV) energy, and cleaning the lithography mask.

Abstract: A resistive memory cell includes a switch and a resistive switching device. The switch includes a first terminal connected to a select line and a gate terminal connected to a word line. The resistive switching device is connected between a second terminal of the switch and a bit line. The resistive switching device is resettable by having a positive bias applied to the word line and a negative bias applied to the bit line.

Abstract: Disclosed herein is a method forming a device comprising forming a high-k layer over a substrate and applying a dry plasma treatment to the high-k layer and removing at least a portion of one or more impurity types from the high-k layer. The dry plasma treatment may be chlorine, fluorine or oxygen plasma treatment. A cap layer may be applied on the high-k layer and a metal gate formed on the cap layer. An interfacial layer may optionally be formed on the substrate, with the high-k layer is formed on the interfacial layer. The high-k layer may have a dielectric constant greater than 3.9, and the cap layer may optionally be titanium nitride. The plasma treatment may be applied after the high-k layer is applied and before the cap layer is applied or after the cap layer is applied.

Abstract: A die includes a plurality of rows of standard cells. Each of all standard cells in the plurality of rows of standard cells includes a transistor and a source edge, wherein a source region of the transistor is adjacent to the source edge. No drain region of any transistor in the each of all standard cells is adjacent to the source region.

Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate of a first semiconductor material; shallow trench isolation (STI) features formed in the semiconductor substrate; and a fin-like active region of a second semiconductor material epitaxy grown on the semiconductor substrate. The first semiconductor material has a first lattice constant and the second semiconductor material has a second lattice constant different from the first lattice constant. The fin-like active region further includes fluorine species.

Abstract: The invention relates to integrated circuit fabrication, and more particularly to a semiconductor device with an electrode. An exemplary structure for a semiconductor device comprises a semiconductor substrate; an electrode over the semiconductor substrate, wherein the electrode comprises a trench in an upper portion of the electrode; and a dielectric feature in the trench.

Abstract: A sense amplifier comprises a cross coupled pair of inverters, a first transistor, a second transistor, and a capacitive device. The cross coupled pair of inverters includes a first end, a second end, and a third end. The first end is configured to receive a first supply voltage. The second end is coupled with a first terminal of the capacitive device and a first terminal of the first transistor. The third end is coupled with a second terminal of the capacitive device and a first terminal of the second transistor. A second terminal of the first transistor and a second terminal of the second transistor are coupled together and are configured to receive a first control signal. A third terminal of the first transistor and a third terminal of the second transistor are coupled together and are configured to receive a second supply voltage different from the first supply voltage.

Abstract: An integrated circuit includes a semiconductor substrate, and an insulation region extending from a top surface of the semiconductor substrate into the semiconductor substrate. An Inter-Layer Dielectric (ILD) is overlying the insulation region. A capacitor includes a first capacitor plate including a first slot contact plug, and a second capacitor plate including a second slot contact plug. The first and the second contact plugs include portions in the ILD. A portion of the ILD between vertical surfaces of the first slot contact plug and the second slot contact plug acts as a capacitor insulator of the capacitor.

Abstract: A method and structure for bump-on-trace bonding is provided. In an embodiment traces to be used for bump-on-trace (BOT) bonding are protected during a pre-solder treatment. The pre-solder treatment improves the adhesion between the exposed traces (e.g., the non-BOT traces) and a solder resist layer.

Abstract: The present disclosure provides a biosensor device wafer testing and processing methods, system and apparatus. The biosensor device wafer includes device areas separated by scribe lines. A number of test areas that allow fluidic electrical testing are embedded in scribe lines or in device areas. An integrated electro-microfluidic probe card includes a fluidic mount that may be transparent, a microfluidic channels in the fluidic mount in a testing portion, at least one microfluidic probe and a number of electronic probe tips at the bottom of the fluidic mount, fluidic and electronic input and output ports on the sides of the fluidic mount, and at least one handle lug on the fluidic mount. The method includes aligning a wafer, mounting the integrated electro-microfluidic probe card, flowing one or more test fluids in series, and measuring and analyzing electrical properties to determine process qualities and an acceptance level of the wafer.

Abstract: A device includes a substrate and insulation regions over a portion of the substrate. A first semiconductor region is between the insulation regions and having a first conduction band. A second semiconductor region is over and adjoining the first semiconductor region, wherein the second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin. The semiconductor fin has a tensile strain and has a second conduction band lower than the first conduction band. A third semiconductor region is over and adjoining a top surface and sidewalls of the semiconductor fin, wherein the third semiconductor region has a third conduction band higher than the second conduction band.