Patents by Inventor Takaharu Tsuji
Takaharu Tsuji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6584022Abstract: The semiconductor memory device includes a memory cell array, a normal data line pair, a redundant data line pair and a data line switch circuit. The data line switch circuit includes an IO shift decoder decoding the column address and the position information related to a defective data line, and an IO select unit shifting the connection between a data input/output pin and a data line while replacing the defective data line according to the decoded result. High speed data transfer is realized by carrying out simultaneously data line selection and redundancy selection according to the column address.Type: GrantFiled: October 9, 2001Date of Patent: June 24, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Takaharu Tsuji
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Publication number: 20030043648Abstract: In a shift switch circuit for replacing a data line, a transmission gate circuit connecting node N2 corresponding to ith write data line to node N4 corresponding to ith read data line is provided. An operation of the shift switch circuit can be confirmed according to whether or not an output corresponding to provided data input signal D<i> is observed as data output signal Q<i>. Preferably, a transmission gate connecting i+1th write data line to an output data line is further provided, in order to further ensure operation confirmation. When a fuse circuit is set to replace a data line, ratio of successful chip repairing will be higher.Type: ApplicationFiled: April 15, 2002Publication date: March 6, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventor: Takaharu Tsuji
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Publication number: 20030007296Abstract: An internal power supply potential generation circuit includes an overcharge prevention circuit connected to an internal power supply node. The overcharge prevention circuit includes a circuit outputting a signal to be determined that is determined by an internal power supply potential, a differential amplification circuit amplifying a difference in potential between the signal to be determined and a reference potential for output to a node as a signal indicating that current should be drawn, and a current draw circuit drawing current from the internal power supply node in response to the signal indicating that current should be drawn. Thus the semiconductor integrated circuit device of interest can provide a steady internal power supply potential.Type: ApplicationFiled: March 12, 2002Publication date: January 9, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Shigeki Tomishima, Mitsutaka Niiro, Masanao Maruta, Hiroshi Kato, Masatoshi Ishikawa, Takaharu Tsuji, Hideto Hidaka, Hiroaki Tanizaki, Tsukasa Ooishi
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Publication number: 20020188898Abstract: A terminating circuit for terminating a common data bus to a predetermined voltage level is inactivated in a test mode, a level detection circuit detects a potential of an internal test data bus line coupled to the common data bus line, and an output state of a ternary output circuit is controlled in accordance with a detection result. In a semiconductor integrated circuit device including the memory integrated together with a logic on a common semiconductor substrate, it is accurately determined whether the output state of the memory is a ternary state while operating the memory under actual operation conditions.Type: ApplicationFiled: May 2, 2002Publication date: December 12, 2002Applicant: Mitsubishi Denki Kabushiki KaishaInventor: Takaharu Tsuji
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Publication number: 20020163845Abstract: A logic portion outputs to a DRAM portion a start address and an end address indicating a memory region where data to be stored is present prior to transition to power down mode having reduced current consumption. In the power down mode, a refresh control unit holds the start address and the end address and controls refresh to be carried out for data only in a region requiring refresh. The power supply of the logic portion is set in off state in the power down mode and accordingly a semiconductor device can consume reduced current while holding data.Type: ApplicationFiled: June 13, 2002Publication date: November 7, 2002Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Tsukasa Ooishi, Takaharu Tsuji, Masatoshi Ishikawa, Hideto Hidaka, Hiroshi Kato
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Patent number: 6466509Abstract: First and second memory banks are provided with M memory blocks each having first and second memory regions, M representing an even number of no less than two, and (M+1) sense amplifier bands arranged on opposite sides of each memory block, and have first and second select lines arranged therefor to select the first and second memory regions, respectively, the first select line being connected to an odd-numbered sense amplifier band of the first memory bank and an even-numbered sense amplifier band of the second memory bank, the second select line being connected to an even-numbered sense amplifier band of the first memory bank and an odd-numbered sense amplifier band of the second memory bank.Type: GrantFiled: January 18, 2002Date of Patent: October 15, 2002Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Engineering Company LimitedInventors: Hiroaki Tanizaki, Shigeki Tomishima, Mitsutaka Niiro, Masanao Maruta, Hiroshi Kato, Masatoshi Ishikawa, Takaharu Tsuji, Hideto Hidaka, Tsukasa Ooishi
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Patent number: 6414894Abstract: A logic portion outputs to a DRAM portion a start address and an end address indicating a memory region where data to be stored is present prior to transition to power down mode having reduced current consumption. In the power down mode, a refresh control unit holds the start address and the end address and controls refresh to be carried out for data only in a region requiring refresh. The power supply of the logic portion is set in off state in the power down mode and accordingly a semiconductor device can consume reduced current while holding data.Type: GrantFiled: February 7, 2001Date of Patent: July 2, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tsukasa Ooishi, Takaharu Tsuji, Masatoshi Ishikawa, Hideto Hidaka, Hiroshi Kato
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Patent number: 6411563Abstract: In accordance with externally applied data and a control signal, a logic circuit performs an arithmetic operation on the data to produce a control signal corresponding to either an SDRAM operation mode or an EDO-DRAM operation mode. A controller receives the control signal from the logic circuit, and produces a general-purpose SDRAM control signal for applying it to a DRAM core. The DRAM core includes a plurality of decoder circuits provided corresponding to the operation modes for decoding the corresponding control signals to produce internal control signals for a memory cell array, respectively.Type: GrantFiled: March 22, 2001Date of Patent: June 25, 2002Assignees: Mitsubishi Denki Kabushiki Kaisha, Matsushita Electric Industrial Col, Ltd.Inventors: Takaharu Tsuji, Toshiaki Kawasaki
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Patent number: 6411560Abstract: A first power supply voltage is supplied to a power supply node of a sense amplifier. A bit line driver outputs a column select signal composed of a second power supply voltage to the gate terminals of N channel MOS transistors of a GIO line gate circuit. When input/output data is [1], a third power supply voltage lower than the first power supply voltage is supplied onto a global data line. In this case, with a threshold voltage of N channel MOS transistors used, a relation is established: second power supply voltage≦third power supply voltage+threshold voltage. As a result, a leakage current can be reduced in a semiconductor memory device driven by plural power supply voltages with respective different voltage levels.Type: GrantFiled: November 14, 2001Date of Patent: June 25, 2002Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Engineering Company LimitedInventors: Hiroaki Tanizaki, Shigeki Tomishima, Mitsutaka Niiro, Masanao Maruta, Hiroshi Kato, Masatoshi Ishikawa, Takaharu Tsuji, Hideto Hidaka, Tsukasa Ooishi
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Patent number: 6384674Abstract: Provided is a power supply-to-power supply capacitance cell including a first capacitor connected between a sub power supply line and a sub ground line, a second capacitor connected between a main power supply line and the sub ground line, and a third capacitor connected between the sub power supply line and a main ground line. Thus, a voltage drop of the sub power supply line can be reduced in current consumption of an internal circuit, so that an operation of the internal circuit is stabilized and the operating speed thereof is improved.Type: GrantFiled: July 15, 1999Date of Patent: May 7, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hiroaki Tanizaki, Tsukasa Ooishi, Shigeki Tomishima, Masatoshi Ishikawa, Hideto Hidaka, Takaharu Tsuji
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Patent number: 6373315Abstract: In a signal potential conversion circuit of a DRAM, a first P channel MOS transistor for charging a first node is connected in parallel with a second P channel MOS transistor and the second P channel MOS transistor is turned on in a pulse manner in response to a rising edge of an input signal. Further, the first P channel MOS transistor has its current drive ability defined to be approximately one-tenth of that of an N channel MOS transistor for discharging the first node. Accordingly, each of the first node and a second node can be charged and discharged quickly to enable conversion of a signal potential to be accomplished speedily.Type: GrantFiled: February 28, 2001Date of Patent: April 16, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Takaharu Tsuji, Shigeki Tomishima, Tsukasa Ooishi
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Publication number: 20020031035Abstract: In a semiconductor memory device with a plurality of banks having a plurality of memory sub array, according to a mode setting signal, data access control is made depending on whether access is made on a memory sub array basis or a bank basis. A multi-bank semiconductor memory device is provided capable of easily implementing both of a low power consumption mode and a long page size mode.Type: ApplicationFiled: February 26, 2001Publication date: March 14, 2002Applicant: Mitsubishi Denki Kabushiki Kaisha Matsushita Electric Industrial Co., Ltd.Inventors: Takaharu Tsuji, Akinori Shibayama
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Publication number: 20020024879Abstract: In accordance with externally applied data and a control signal, a logic circuit performs an arithmetic operation on the data to produce a control signal corresponding to either an SDRAM operation mode or an EDO-DRAM operation mode. A controller receives the control signal from the logic circuit, and produces a general-purpose SDRAM control signal for applying it to a DRAM core. The DRAM core includes a plurality of decoder circuits provided corresponding to the operation modes for decoding the corresponding control signals to produce internal control signals for a memory cell array, respectively.Type: ApplicationFiled: March 22, 2001Publication date: February 28, 2002Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA, AND MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Takaharu Tsuji, Toshiaki Kawasaki
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Publication number: 20020021593Abstract: A semiconductor memory device that can transfer data at high speed is provided. The semiconductor memory device includes a memory cell array, a normal data line pair, a redundant data line pair and a data line switch circuit. The data line switch circuit includes an IO shift decoder decoding the column address and the position information related to a defective data line, and an IO select unit shifting the connection between a data input/output pin and a data line while replacing the defective data line according to the decoded result. High speed data transfer is realized by carrying out simultaneously data line selection and redundancy selection according to the column address.Type: ApplicationFiled: January 25, 2001Publication date: February 21, 2002Applicant: Mitsubishi Denki Kabushiki KaishaInventor: Takaharu Tsuji
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Publication number: 20020021600Abstract: The semiconductor memory device includes a memory cell array, a normal data line pair, a redundant data line pair and a data line switch circuit. The data line switch circuit includes an IO shift decoder decoding the column address and the position information related to a defective data line, and an IO select unit shifting the connection between a data input/output pin and a data line while replacing the defective data line according to the decoded result. High speed data transfer is realized by carrying out simultaneously data line selection and redundancy selection according to the column address.Type: ApplicationFiled: October 9, 2001Publication date: February 21, 2002Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventor: Takaharu Tsuji
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Publication number: 20020000873Abstract: Provided is a power supply-to-power supply capacitance cell including a first capacitor connected between a sub power supply line and a sub ground line, a second capacitor connected between a main power supply line and the sub ground line, and a third capacitor connected between the sub power supply line and a main ground line. Thus, a voltage drop of the sub power supply line can be reduced in current consumption of an internal circuit, so that an operation of the internal circuit is stabilized and the operating speed thereof is improved.Type: ApplicationFiled: July 15, 1999Publication date: January 3, 2002Inventors: HIROAKI TANIZAKI, TSUKASA OOISHI, SHIGEKI TOMISHIMA, MASATOSHI ISHIKAWA, HIDETO HIDAKA, TAKAHARU TSUJI
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Publication number: 20010045859Abstract: In a signal potential conversion circuit of a DRAM, a first P channel MOS transistor for charging a first node is connected in parallel with a second P channel MOS transistor and the second P channel MOS transistor is turned on in a pulse manner in response to a rising edge of an input signal. Further, the first P channel MOS transistor has its current drive ability defined to be approximately one-tenth of that of an N channel MOS transistor for discharging the first node. Accordingly, each of the first node and a second node can be charged and discharged quickly to enable conversion of a signal potential to be accomplished speedily.Type: ApplicationFiled: February 28, 2001Publication date: November 29, 2001Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Takaharu Tsuji, Shigeki Tomishima, Tsukasa Ooishi
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Publication number: 20010045579Abstract: A logic portion outputs to a DRAM portion a start address and an end address indicating a memory region where data to be stored is present prior to transition to power down mode having reduced current consumption. In the power down mode, a refresh control unit holds the start address and the end address and controls refresh to be carried out for data only in a region requiring refresh. The power supply of the logic portion is set in off state in the power down mode and accordingly a semiconductor device can consume reduced current while holding data.Type: ApplicationFiled: February 7, 2001Publication date: November 29, 2001Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Tsukasa Ooishi, Takaharu Tsuji, Masatoshi Ishikawa, Hideto Hidaka, Hiroshi Kato
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Patent number: 6118710Abstract: In a semiconductor memory device, replacement is possible with a redundant cell in the same or different memory sub array in a mode other than a particular test mode. A redundancy determining circuit inactivates a spare word line enable signal corresponding to a redundant cell when a disturb refresh acceleration mode test is designated. An SWL driver renders a spare word line non-selective in response to the spare word line enable signal. An NWL driver simultaneously activates a plurality of word lines (except a word line corresponding to a defective cell) in response to a word line enable signal output from the redundancy determining circuit.Type: GrantFiled: November 19, 1998Date of Patent: September 12, 2000Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Takaharu Tsuji
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Patent number: 6058053Abstract: In the semiconductor memory device, independent from redundancy determination by a redundancy determining circuit, a word line activating signal (subdecode signal) for setting a word line in a normal block corresponding to a decoded address signal, is activated. A WL driver includes a driver portion for selecting a word line in the normal block, and a driver portion for selecting a spare word line in a redundant block. When redundancy is not to be used as a result of redundancy determination by the redundancy determining circuit, activated subdecode signal is inactivated. If redundancy is to be used as a result of redundancy determination, a corresponding word line is set to the selected state, using the activated subdecode signal. Thus a semiconductor memory device in which substitution can be done at high speed with high efficiency is provided.Type: GrantFiled: November 18, 1998Date of Patent: May 2, 2000Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Takaharu Tsuji, Tsukasa Ooishi, Hiroshi Kato, Shigeki Tomishima, Hiroki Shimano