Abstract: Row decoders RD are provided corresponding to memory blocks, respectively. Row decoders RD each operate receiving an operating power supply voltage from a hierarchical power supply system constituted of a main power supply line and a sub power supply line. With the use of a bank activation signal ACT, the main power supply line and the sub power supply line for all the hierarchical power supply system short circuit and a voltage of the sub power supply line is recovered. Thereafter, the main power supply line and the sub power supply line are cut off for a row decoder RD of a non-selected memory block based on a block selection signal BS supplied through a decoding operation.

Abstract: A shot region includes a device region for forming a semiconductor device therein and a dicing region used for dicing. A portion of the peripheral edge portion of the shot region is defined by a portion of the peripheral edge portion of the device region. An alignment mark is arranged within the device region, and additional alignment marks are arranged within the dicing region. Thus, the number of the devices manufactured per wafer can be increased without degrading precision of alignment.

Abstract: A semiconductor memory device that operates in various modes such as in a normal operation mode and a disturb accelerated test mode in which two word lines are activated simultaneously, includes a boosting power supply circuit, a boosted voltage supply line, and an input terminal connected to the boosted voltage supply line. In a disturb accelerated test mode or in a burn-in test mode, an external voltage is supplied from an external power supply to the input terminal. A word line is reliably boosted in voltage in a disturb accelerated test mode.

Abstract: A semiconductor memory device operates switched between a first readout mode in which data readout according to a specified activation of a column address strobe signal /CAS that shows a transition in synchronization with an external clock signal is output during a period including the specified activation of signal /CAS, and a second readout mode in which the readout data is output during a subsequent predetermined period of signal /CAS. A control circuit for controlling the data output timing from an output buffer activates the output buffer at an elapse of a predetermined time following the specified activation of signal /CAS in the first readout mode. In the second readout mode, the control circuit activates the output buffer according to activation of signal /CAS at a predetermined period.

Abstract: A substrate voltage detecting circuit includes a detection node, a transistor responsive to a detected substrate voltage for changing a comparison voltage, a differential amplifier for comparing the comparison voltage with a prescribed reference voltage and outputting an enable signal when the comparison voltage exceeds the reference voltage, and a transistor turned on in response to the enable signal for fixing the reference voltage at an L level. The internal voltage detecting circuit further includes transistors for reducing current consumption. Consequently, the responsibility thereof is improved even with small power consumption.

Abstract: A shot region includes a device region for forming a semiconductor device therein and a dicing region used for dicing. A portion of the peripheral edge portion of the shot region is defined by a portion of the peripheral edge portion of the device region. An alignment mark is arranged within the device region, and additional alignment marks are arranged within the dicing region. Thus, the number of the devices manufactured per wafer can be increased without degrading precision of alignment.