Patents by Inventor Takahiro Kawano

Takahiro Kawano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9203306
    Abstract: In a digital control power supply, a mode control unit measures a first frequency and a second frequency for a difference between a second digital value and a target value. Based on the measured first frequency and second frequency and a predetermined threshold set to the first and second frequencies, the mode control unit determines whether an amplification factor for use in amplification processing by an amplifier is maintained at a current amplification factor or is changed to an amplification factor which is larger or smaller by 1 than the current amplification factor. This contributes to an improvement in noise resistance of the digital control power supply and prevents an output voltage from being unstable.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: December 1, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Takahiro Kawano
  • Patent number: 9197286
    Abstract: An apparatus includes: an offset adjustment unit supplying an offset correction signal corresponding to a frequency switching to an adder unit receiving output from a mixer; a timing adjustment unit adjusting the timing of a frequency switching signal supplied to a local oscillator and the timing of an offset correction amount switching signal supplied to the offset adjustment unit for changing an offset amount in correspondence with the frequency switching in the local oscillator; a noise amount measurement and calculation unit receiving a signal obtained by amplifying and filtering the signal from the adder unit, to measure a noise amount of the signal and generates a timing determination signal based on the noise amount; and a control unit controlling frequency switching signal timing and the offset correction amount switching signal supplied to the timing adjustment unit, based on the timing determination signal from the noise amount measurement and calculation unit.
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: November 24, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Takahiro Kawano
  • Publication number: 20150273649
    Abstract: A polishing apparatus which can reduce scratches that are generated on a surface of a substrate during polishing by detecting a foreign matter such as a fragment of the substrate on an inner circumferential surface of a retaining ring for holding an edge portion (peripheral portion) of the substrate is disclosed. The polishing apparatus includes a polishing table having a polishing surface, and a top ring having a substrate holding surface to hold a beck surface of a substrate and a retaining ring to retain the substrate on the substrate holding surface. The top ring holds the substrate and presses the substrate against the polishing surface. The polishing apparatus includes an imaging device configured to image an inner circumferential surface of the retaining ring, and an image processor configured to process an image obtained by the imaging device to judge whether there is a foreign matter on the inner circumferential surface of the retaining ring.
    Type: Application
    Filed: March 25, 2015
    Publication date: October 1, 2015
    Inventors: Ryuichi KOSUGE, Hiroshi SOTOZAKI, Takahiro KAWANO, Akihiro MOCHIDA
  • Patent number: 9142667
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes: forming a plurality of trenches; forming a gate insulating film; burying a gate electrode; burying an insulating member; projecting the insulating member; forming a base layer; forming a mask film; forming a first semiconductor layer; forming a carrier ejection layer; forming a first electrode; and forming a second electrode. The projecting includes projecting the insulating member from the upper surface of the semiconductor substrate by removing an upper layer portion of the semiconductor substrate. The mask film is formed so as to cover the projected insulating member. The forming the first semiconductor layer includes forming a first semiconductor layer of the first conductivity type in an upper layer portion of the base layer by doping the base layer with impurity, the upper layer portion having a lower surface below an upper end of the gate electrode.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: September 22, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideki Okumura, Hiroto Misawa, Takahiro Kawano
  • Publication number: 20150028413
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes: forming a plurality of trenches; forming a gate insulating film; burying a gate electrode; burying an insulating member; projecting the insulating member; forming a base layer; forming a mask film; forming a first semiconductor layer; forming a carrier ejection layer; forming a first electrode; and forming a second electrode. The projecting includes projecting the insulating member from the upper surface of the semiconductor substrate by removing an upper layer portion of the semiconductor substrate. The mask film is formed so as to cover the projected insulating member. The forming the first semiconductor layer includes forming a first semiconductor layer of the first conductivity type in an upper layer portion of the base layer by doping the base layer with impurity, the upper layer portion having a lower surface below an upper end of the gate electrode.
    Type: Application
    Filed: September 12, 2014
    Publication date: January 29, 2015
    Inventors: Hideki OKUMURA, Hiroto MISAWA, Takahiro KAWANO
  • Publication number: 20150015228
    Abstract: In a digital control power supply, a mode control unit measures a first frequency and a second frequency for a difference between a second digital value and a target value. Based on the measured first frequency and second frequency and a predetermined threshold set to the first and second frequencies, the mode control unit determines whether an amplification factor for use in amplification processing by an amplifier is maintained at a current amplification factor or is changed to an amplification factor which is larger or smaller by 1 than the current amplification factor. This contributes to an improvement in noise resistance of the digital control power supply and prevents an output voltage from being unstable.
    Type: Application
    Filed: September 29, 2014
    Publication date: January 15, 2015
    Applicant: Renesas Electronics Corporation
    Inventor: Takahiro KAWANO
  • Publication number: 20140354461
    Abstract: A semiconductor device includes an analog-digital converter circuit. The analog-digital converter circuit includes a delay cell array and an encoder. The delay cell array contains n number of serially-coupled delay cells, receives a reference clock signal, and utilizes an analog input signal as the power supply voltage for the delay cells in each stage. The encoder encodes an output signal from the delay cell in each stage for the delay cell array and outputs the encoded output signal as a digital output signal. The n number of delay cells includes delay quantities weighted for each delay cell. The encoder encodes the output signal of the delay cells in each stage for the delay cell array by weighting corresponding to the number of delay cell stage.
    Type: Application
    Filed: May 1, 2014
    Publication date: December 4, 2014
    Applicant: Renesas Electronics Corporation
    Inventor: Takahiro Kawano
  • Publication number: 20140348209
    Abstract: An apparatus includes: an offset adjustment unit supplying an offset correction signal corresponding to a frequency switching to an adder unit receiving output from a mixer; a timing adjustment unit adjusting the timing of a frequency switching signal supplied to a local oscillator and the timing of an offset correction amount switching signal supplied to the offset adjustment unit for changing an offset amount in correspondence with the frequency switching in the local oscillator; a noise amount measurement and calculation unit receiving a signal obtained by amplifying and filtering the signal from the adder unit, to measure a noise amount of the signal and generates a timing determination signal based on the noise amount; and a control unit controlling frequency switching signal timing and the offset correction amount switching signal supplied to the timing adjustment unit, based on the timing determination signal from the noise amount measurement and calculation unit.
    Type: Application
    Filed: August 8, 2014
    Publication date: November 27, 2014
    Inventor: Takahiro KAWANO
  • Patent number: 8890237
    Abstract: A power semiconductor device according to one embodiment includes a first electrode, a semiconductor substrate provided on the first electrode, and an insulating member. A terminal trench is made in the upper surface of the semiconductor substrate in a region including a boundary between a cell region and a terminal region. The semiconductor substrate includes a first portion of a first conductivity type and connected to the first electrode, a second portion of the first conductivity type, a third portion of a second conductivity type provided on the second portion in the cell region and connected to the second electrode, and a fourth portion of the first conductivity type selectively provided on the third portion and connected to the second electrode. The insulating member is disposed between the third portion and the second portion in a direction from the cell region toward the terminal region.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: November 18, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takahiro Kawano, Hideki Okumura
  • Patent number: 8878507
    Abstract: In a digital control power supply, a mode control unit measures a first frequency and a second frequency for a difference between a second digital value and a target value. Based on the measured first frequency and second frequency and a predetermined threshold set to the first and second frequencies, the mode control unit determines whether an amplification factor for use in amplification processing by an amplifier is maintained at a current amplification factor or is changed to an amplification factor which is larger or smaller by 1 than the current amplification factor. This contributes to an improvement in noise resistance of the digital control power supply and prevents an output voltage from being unstable.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: November 4, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Takahiro Kawano
  • Patent number: 8859365
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes: forming a plurality of trenches; forming a gate insulating film; burying a gate electrode; burying an insulating member; projecting the insulating member; forming a base layer; forming a mask film; forming a first semiconductor layer; forming a carrier ejection layer; forming a first electrode; and forming a second electrode. The projecting includes projecting the insulating member from the upper surface of the semiconductor substrate by removing an upper layer portion of the semiconductor substrate. The mask film is formed so as to cover the projected insulating member. The forming the first semiconductor layer includes forming a first semiconductor layer of the first conductivity type in an upper layer portion of the base layer by doping the base layer with impurity, the upper layer portion having a lower surface below an upper end of the gate electrode.
    Type: Grant
    Filed: March 3, 2014
    Date of Patent: October 14, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideki Okumura, Hiroto Misawa, Takahiro Kawano
  • Patent number: 8824608
    Abstract: An apparatus includes: an offset adjustment unit supplying an offset correction signal corresponding to a frequency switching to an adder unit receiving output from a mixer; a timing adjustment unit adjusting the timing of a frequency switching signal supplied to a local oscillator and the timing of an offset correction amount switching signal supplied to the offset adjustment unit for changing an offset amount in correspondence with the frequency switching in the local oscillator; a noise amount measurement and calculation unit receiving a signal obtained by amplifying and filtering the signal from the adder unit, to measure a noise amount of the signal and generates a timing determination signal based on the noise amount; and a control unit controlling frequency switching signal timing and the offset correction amount switching signal supplied to the timing adjustment unit, based on the timing determination signal from the noise amount measurement and calculation unit.
    Type: Grant
    Filed: January 24, 2013
    Date of Patent: September 2, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Takahiro Kawano
  • Publication number: 20140179075
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes: forming a plurality of trenches; forming a gate insulating film; burying a gate electrode; burying an insulating member; projecting the insulating member; forming a base layer; forming a mask film; forming a first semiconductor layer; forming a carrier ejection layer; forming a first electrode; and forming a second electrode. The projecting includes projecting the insulating member from the upper surface of the semiconductor substrate by removing an upper layer portion of the semiconductor substrate. The mask film is formed so as to cover the projected insulating member. The forming the first semiconductor layer includes forming a first semiconductor layer of the first conductivity type in an upper layer portion of the base layer by doping the base layer with impurity, the upper layer portion having a lower surface below an upper end of the gate electrode.
    Type: Application
    Filed: March 3, 2014
    Publication date: June 26, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hideki OKUMURA, Hiroto MISAWA, Takahiro KAWANO
  • Patent number: 8740681
    Abstract: A game machine is provided that displays an attack direction in a 3D virtual game space when a player character is attacked, such that the human player can readily recognize the attack direction. In the game machine that activates the player character and an enemy character that attacks the player character in a 3D virtual game space, the direction of the attack received by the player character from the enemy character is acquired based on player position information indicating the position of the player character and enemy position information indicating the position of the enemy character in the game space. Damage marks which are objects that indicate the attack direction are generated at positions corresponding to the attack direction in a player region set around the player character, and at least a part of the game space, including the player character and the damage marks, is displayed.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: June 3, 2014
    Assignee: Capcom Co., Ltd.
    Inventors: Takahiro Kawano, Hidenori Kouyama, Kenta Yamaki
  • Patent number: 8740682
    Abstract: A game machine is provided that displays an attack direction in a 3D virtual game space when a player character is attacked, such that the human player can readily recognize the attack direction. In the game machine that activates the player character and an enemy character that attacks the player character in a 3D virtual game space, the direction of the attack received by the player character from the enemy character is acquired based on player position information indicating the position of the player character and enemy position information indicating the position of the enemy character in the game space. Damage marks which are objects that indicate the attack direction are generated at positions corresponding to the attack direction in a player region set around the player character, and at least a part of the game space, including the player character and the damage marks, is displayed.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: June 3, 2014
    Assignee: Capcom Co., Ltd.
    Inventors: Takahiro Kawano, Hidenori Kouyama, Kenta Yamaki
  • Patent number: 8710582
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes: forming a plurality of trenches; forming a gate insulating film; burying a gate electrode; burying an insulating member; projecting the insulating member; forming a base layer; forming a mask film; forming a first semiconductor layer; forming a carrier ejection layer; forming a first electrode; and forming a second electrode. The projecting includes projecting the insulating member from the upper surface of the semiconductor substrate by removing an upper layer portion of the semiconductor substrate. The mask film is formed so as to cover the projected insulating member. The forming the first semiconductor layer includes forming a first semiconductor layer of the first conductivity type in an upper layer portion of the base layer by doping the base layer with impurity, the upper layer portion having a lower surface below an upper end of the gate electrode.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: April 29, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideki Okumura, Hiroto Misawa, Takahiro Kawano
  • Patent number: 8679234
    Abstract: An object of the present invention is to provide a heavy metal removing apparatus which can efficiently remove the heavy metal contained in the dust produced by burning of the raw material containing the heavy metal, and a cement production system comprising the heavy metal removing apparatus. The heavy metal removing apparatus 10 comprises a cyclone separator 11 which separates exhaust gas containing the heavy metal from a part of the dust heated to a temperature equal to or more than a temperature at which the heavy metal can volatilize, a bag filter 13 which is connected to the subsequent stage of the cyclone separator 11 and separates the exhaust gas containing the heavy metal from the remainder of the dust, and a heavy metal removal tower 14 which is connected to the subsequent stage of the bag filter and removes the heavy metal from the exhaust gas.
    Type: Grant
    Filed: January 22, 2009
    Date of Patent: March 25, 2014
    Assignee: Taiheiyo Cement Corporation
    Inventors: Kazuhiko Soma, Takahiro Kawano, Tokuhiko Shirasaka, Hidenori Isoda, Osamu Yamaguchi
  • Publication number: 20140077292
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate including a drain layer of a first conductivity type and a base layer of a second conductivity type provided on the drain layer, a gate electrode including a first portion formed in the semiconductor substrate, a gate insulating layer provided between the gate electrode and the semiconductor substrate, an upper insulating layer formed on the gate electrode, a source layer of the first conductivity type that is provided on a sidewall of the upper insulating layer and whose width increases towards the base layer, and a source electrode provided on the source layer.
    Type: Application
    Filed: March 22, 2013
    Publication date: March 20, 2014
    Inventors: Takuya NOGAMI, Hideki OKUMURA, Takahiro KAWANO
  • Publication number: 20130248995
    Abstract: A semiconductor device includes a first semiconductor layer of a first conductivity type, a base layer of a second conductivity type placed above the first semiconductor layer, a second semiconductor layer of the first conductivity type placed above the base layer, multiple gate electrodes having upper end is positioned above the upper surface of the base layer, a lower end positioned below the bottom of the base layer, and contacting the first semiconductor layer, the second semiconductor layer, and the base layer through a gate insulating film, insulating component arranged above the gate electrode in which the upper surface is positioned below the upper surface of the second semiconductor layer, and a conductive layer covering the second semiconductor layer from the upper end to the bottom end.
    Type: Application
    Filed: September 7, 2012
    Publication date: September 26, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsuya NISHIWAKI, Tsuyoshi Ota, Norio Yasuhara, Masatoshi Arai, Takahiro Kawano
  • Publication number: 20130221431
    Abstract: A method for manufacturing a semiconductor device includes forming a first insulating film on inner surfaces of trenches arranged in parallel in a semiconductor layer, forming a control electrode on the first insulating film, and forming a second insulating film on the control electrode, where the upper surface of the second insulating film is lower than the upper end of the first insulating film. In addition, the method includes etching the semiconductor layer to a depth near the upper end of the control electrode and forming a first semiconductor region. The method further includes forming a conductive film and then a second semiconductor region in the upper portion of the first semiconductor region by diffusion of impurities from the conductive film into the upper portion of the first semiconductor region, and forming a contact hole by etching back the conductive layer.
    Type: Application
    Filed: September 6, 2012
    Publication date: August 29, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yuta MUSHA, Takayuki SAKAI, Hideki OKUMURA, Takahiro KAWANO