Patents by Inventor Takahiro Kawashima

Takahiro Kawashima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120016261
    Abstract: A hollow microtube structure capable of being used as a minimally invasive electrode, a production method thereof, and a biopsy device using the hollow microtube structure. The hollow microtube structure includes a semiconductor substrate and at least one hollow tube formed on a surface of the semiconductor substrate. The hollow tube includes a metal coating film layer on the inner surface and an electrically insulating coating film layer on the outer surface. The semiconductor substrate includes a through hole communicated with an interior of a hollow tube at a location where the hollow tube is formed. The production method includes an etching, a sacrificial layer forming, a metal coating film layer forming, an electrically insulating coating film layer forming, a tip portion removing, and a piercing.
    Type: Application
    Filed: March 19, 2010
    Publication date: January 19, 2012
    Applicant: NAT. UNIV. CORP. TOYOHASHI UNIV. OF TECHNOLOGY
    Inventors: Makoto Ishida, Takeshi Kawano, Takahiro Kawashima, Kuniharu Takei
  • Publication number: 20110318891
    Abstract: A method of crystallizing a silicon thin film, which enables uniforming the size of a crystalline grain of the silicon thin film, includes: a second process of stacking, on a substrate, a first gate electrode having a first reflectivity; a third process of stacking a second gate electrode on the first gate electrode, the second gate electrode having a second reflectivity lower than the first reflectivity and including a top face having an area smaller than an area of the top face of the first gate electrode; a fourth process of stacking a gate insulation film to cover a first region and a second region; a fifth process of stacking a noncrystalline silicon thin film on the stacked gate insulation film; and a sixth process of crystallizing the noncrystalline silicon thin film by irradiating the noncrystalline silicon thin film from above with a laser beam.
    Type: Application
    Filed: September 9, 2011
    Publication date: December 29, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Tomohiko ODA, Takahiro KAWASHIMA
  • Publication number: 20110278583
    Abstract: A thin-film semiconductor device includes, in order, a substrate, a gate electrode, a gate insulating film, a first channel layer, and a second channel layer. The second channel layer includes a protrusion between first top surface end portions. The protrusion has first lateral surfaces that each extend between one of the first top surface end portions and a top surface of the protrusion. An insulation layer is on the top surface of the protrusion. The insulation layer has second lateral surfaces that each extend to one of second top surface end portions of the insulation layer. Two contact layers are each on one of the second top surface end portions of the insulation layer, adjacent one of the second lateral surfaces of the insulation layer, adjacent one of the first lateral surfaces of the protrusion, and on one of the first top surface end portions of the second channel layer. A source electrode is on one of the two contact layers, and a drain electrode is on the other of the two contact layers.
    Type: Application
    Filed: May 25, 2011
    Publication date: November 17, 2011
    Applicants: PANASONIC LIQUID CRYSTAL DISPLAY CO., LTD., PANASONIC CORPORATION
    Inventors: Hiroshi HAYASHI, Takahiro KAWASHIMA, Genshiro KAWACHI
  • Publication number: 20110260789
    Abstract: A variable gain amplifier circuit includes: an operational amplifier having a non-inverting input terminal applied with a predetermined voltage; a feedback resistor having one end connected to an inverting input terminal of the operational amplifier and the other end connected to an output terminal of the operational amplifier; and a variable resistor having one end applied with an input voltage and the other end connected to the inverting input terminal of the operational amplifier.
    Type: Application
    Filed: October 21, 2010
    Publication date: October 27, 2011
    Applicants: SANYO SEMICONDUCTOR CO., LTD., Joint-stock company of Japan, SANYO ELECTRIC CO., LTD., Joint-stock company of Japan
    Inventors: Takahiro Kawashima, Rui Kurihara
  • Publication number: 20110255565
    Abstract: The invention provides a laser light detection circuit that prevents a peak output occurring when the circuit switches between the operation stop mode and the operation mode so as to prevent the breakdown or malfunction of the next-connected circuit. A laser light detection circuit has a differential amplifier that amplifies and outputs a signal corresponding to the intensity of laser light, a drive transistor having a base to which the output of the differential amplifier is applied, a second constant-current source connected to the emitter of the drive transistor, an output transistor having a base connected to the emitter of the drive transistor, a bypass transistor connected between the emitter of the drive transistor and the ground, and a control circuit. The control circuit forms a bypass current route from the second constant-current source to the ground through the bypass transistor by turning on the bypass transistor when the circuit switches from the operation stop mode to the operation mode.
    Type: Application
    Filed: April 14, 2011
    Publication date: October 20, 2011
    Applicant: ON Semiconductor Trading, Ltd.
    Inventors: Rui KURIHARA, Takahiro KAWASHIMA
  • Publication number: 20110244645
    Abstract: A semiconductor device includes: a semiconductor substrate in which a trench is formed; a source region and a drain region each of which is buried in the trench and contains an impurity of the same conductive type; a semiconductor FIN buried in the trench and provided between the source and drain regions; a gate insulating film provided on a side surface of the semiconductor FIN as well as the upper surface of the semiconductor FIN; and a gate electrode formed on the gate insulating film.
    Type: Application
    Filed: June 16, 2011
    Publication date: October 6, 2011
    Applicant: Panasonic Corporation
    Inventors: Junko IWANAGA, Takeshi Takagi, Yoshihiko Kanzawa, Haruyuki Sorada, Tohru Saitoh, Takahiro Kawashima
  • Patent number: 8000182
    Abstract: An integrated circuit for optical disc comprising for each of light-receiving surfaces: an operational amplifier including inverting and noninverting input terminals receiving first and second input voltages, and output terminal receiving output voltage; a feedback resistor connected between the inverting input and output terminals; a photodiode connected between one power supply line of the first and second power supply lines and the inverting input terminal to generate current corresponding to reflected light; a capacitor connected between the one power supply line and the noninverting input terminal; and an input resistor connected between reference power source and the noninverting input terminal, further comprising: an adder adding voltages corresponding to the output voltages to generate RF signal, capacitance of the capacitor and resistance value of the input resistor being determined in accordance with capacitance of parasitic capacitor connected in parallel with the photodiode and resistance value of
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: August 16, 2011
    Assignees: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.
    Inventors: Masashi Arai, Takahiro Kawashima
  • Patent number: 7986002
    Abstract: A semiconductor device includes: a semiconductor substrate in which a trench is formed; a source region and a drain region each of which is buried in the trench and contains an impurity of the same conductive type; a semiconductor FIN buried in the trench and provided between the source and drain regions; a gate insulating film provided on a side surface of the semiconductor FIN as well as the upper surface of the semiconductor FIN; and a gate electrode formed on the gate insulating film.
    Type: Grant
    Filed: March 19, 2004
    Date of Patent: July 26, 2011
    Assignee: Panasonic Corporation
    Inventors: Junko Iwanaga, Takeshi Takagi, Yoshihiko Kanzawa, Haruyuki Sorada, Tohru Saitoh, Takahiro Kawashima
  • Publication number: 20110144936
    Abstract: Provided is a photoelectric smoke sensor capable of correcting a sensitivity according to a state of contamination. The photoelectric smoke sensor includes: a storage section (6) for storing a zero detection value VN and an initial zero detection value; a moving average value calculating section (51) for calculating a moving average value of detection AD values output from a detection portion (1, 2, 3); a zero detection value updating section (52) for calculating a new zero detection value VN when a sensitivity of the detection portion is decreased as compared with that in an initial state, and in addition, when a rate of change in the moving average value with respect to the zero detection value VN exceeds a predetermined value; a detection AD value correcting section (53) for correcting the detection value; and a smoke-density computing section (54) for converting the corrected detection value into smoke-density data.
    Type: Application
    Filed: December 1, 2010
    Publication date: June 16, 2011
    Inventor: Takahiro KAWASHIMA
  • Publication number: 20110090716
    Abstract: In order to achieve an object to reduce a surge voltage and suppress noise generation, the present invention provides a DC-DC converter with a snubber circuit, which boosts a voltage Vi of a DC power supply. The snubber circuit includes: a series circuit connected to both ends of a smoothing capacitor Co and including a snubber capacitor Cs and a snubber resistor Rs; a snubber diode Ds1 connected to a node at which the snubber capacitor Cs and the snubber resistor Rs are connected, and to a node at which a reactor Lr1 and an additional winding 1b of a transformer T1 are connected; and a snubber diode Ds2 connected to the node at which the snubber capacitor Cs and the snubber resistor Rs are connected, and to a node at which a reactor Lr2 and an additional winding 2b of a transformer T2 are connected.
    Type: Application
    Filed: June 15, 2009
    Publication date: April 21, 2011
    Applicants: Sanken Electric Co., Ltd., National University Corporation Shimane University
    Inventors: Hideki Asuke, Hideharu Takano, Mamoru Tsuruya, Masayoshi Yamamoto, Takahiro Kawashima, Shigeyuki Funabiki
  • Patent number: 7923499
    Abstract: Disclosed is calcium carbonate treated with a curing active ingredient, which, when compounded in a rubber, enables to provide good workability (handling) to the rubber and maximize advantageous properties of the rubber attributable to calcium carbonate (e.g., slip resistance) without deteriorating the reinforcing property of the rubber. The calcium carbonated treated with a curing active ingredient is produced by mixing a modified calcium carbonate having its surface treated with a fatty acid or a resin acid and silicic acid and having an average primary particle diameter of 0.01 to 0.5 ?m with a curing active ingredient which takes a liquid form at ambient temperature so that the content of the curing active ingredient in the finished product becomes 9.1 to 35 wt %.
    Type: Grant
    Filed: September 26, 2007
    Date of Patent: April 12, 2011
    Assignee: Shiraishi Kogyo Kaisha, Ltd.
    Inventors: Takahiro Kawashima, Shoichi Tsutsui
  • Publication number: 20100224915
    Abstract: According to a method of the present invention for manufacturing a semiconductor piece, at least two semiconductor layers (12) are first formed on a substrate (10) by stacking a sacrificial layer (11) and the semiconductor layer (12) on the substrate (10) in this order and repeating this stacking. Next, the semiconductor layers (12) are divided into pieces by etching part of the sacrificial layers (11) and part of the semiconductor layers (12). Then, the pieces are separated from the substrate by removing the sacrificial layers (11).
    Type: Application
    Filed: January 12, 2007
    Publication date: September 9, 2010
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Takahiro Kawashima, Tohru Saitoh, Tohru Nakagawa, Hideo Torii
  • Patent number: 7772125
    Abstract: A method for fabricating a structure according to the present invention includes the steps of: forming a groove in a substrate, dropping a solution in which microstructures such as nanowires are dispersed into the groove and the step of evaporating the solution to arrange the microstructures in the groove in a self-organizing manner.
    Type: Grant
    Filed: February 8, 2006
    Date of Patent: August 10, 2010
    Assignee: Panasonic Corporation
    Inventors: Takahiro Kawashima, Tohru Saitoh, Norihisa Mino
  • Publication number: 20100178564
    Abstract: The present invention provides a highly reliable energy storage device capable of preventing a reaction current from flowing in a carbon nanotube electrode by ionizing a catalyst metal or a substrate metal to cause the metal to flow out to an electrolytic solution. An energy storage device of the present invention includes: at least a pair of electrode bodies that are a cathode and an anode; and an electrolytic solution. At least one of the electrode bodies is configured such that a layer of carbon nanotubes is formed on an electric conductor. A coupling region where one ends of the carbon nanotubes are coupled to and electrically connected to the electric conductor and a non-coupling region where ends of the carbon nanotubes are not coupled to the electric conductor are formed on a surface of the electric conductor. The carbon nanotubes having one ends connected to the coupling region are toppled to cover a surface of the non-coupling region.
    Type: Application
    Filed: March 12, 2009
    Publication date: July 15, 2010
    Inventors: Takuma Asari, Hironori Kumagai, Shigeo Hayashi, Yasuhiro Hashimoto, Takahiro Kawashima
  • Publication number: 20100133509
    Abstract: A method for fabricating a semiconductor nanowire that has first and second regions is provided. A catalyst particle is put on a substrate. A first source gas is introduced, thereby growing the first region from the catalyst particle via a vapor-liquid-solid phase growth. A protective coating is formed on a sidewall of the first region, and a second source gas is introduced to grow the second region extending from the first region via the liquid-solid-phase growth.
    Type: Application
    Filed: June 4, 2008
    Publication date: June 3, 2010
    Applicant: PANASONIC CORPORATION
    Inventors: Takahiro Kawashima, Tohru Saitoh
  • Patent number: 7719031
    Abstract: A bipolar transistor 120 comprises a substrate 1, a intrinsic base region 11 and an extrinsic base region 12. The intrinsic base region 11 comprises a silicon buffer layer 109 comprised of silicon which is formed on the substrate 1, and a composition-ratio graded base layer 111 which is formed on the silicon buffer layer and comprises silicon and at least germanium and where a composition ratio of the germanium to the silicon varies in a thickness direction of the composition-ratio graded base layer 111. The extrinsic base region 12 comprises an extrinsic base formation layer 113 comprised of silicon which is formed on the substrate and adjacent to the silicon buffer layer. And the thickness of the extrinsic base formation layer 113 is not less than 40 nm.
    Type: Grant
    Filed: July 6, 2004
    Date of Patent: May 18, 2010
    Assignee: Panasonic Corporation
    Inventors: Tohru Saitoh, Takahiro Kawashima, Ken Idota, Yoshihiko Kanzawa, Teruhito Ohnishi
  • Patent number: 7718995
    Abstract: A nanowire according to the present invention includes: a nanowire body made of a crystalline semiconductor as a first material; and a plurality of fine particles, which are made of a second material, including a constituent element of the semiconductor, and which are located on at least portions of the surface of the nanowire body. The surface of the nanowire body is smooth.
    Type: Grant
    Filed: June 18, 2007
    Date of Patent: May 18, 2010
    Assignee: Panasonic Corporation
    Inventors: Takahiro Kawashima, Tohru Saitoh, Kenji Harada
  • Publication number: 20100019743
    Abstract: The present invention provides a DC-DC converter including a first series circuit connected to both ends of a first switch and formed of a winding of a first transformer, a first reactor, a first diode, and a smoothing capacitor, a second diode connected to a connection point of a primary winding of the first transformer, the winding of the first transformer and the first switch, and to one end of the smoothing capacitor, a second series circuit connected to both ends of a second switch and formed of a winding of a second transformer, a second reactor, a third diode, and the smoothing capacitor, a fourth diode connected to a connection point of a primary winding of the second transformer, the winding of the second transformer and the second switch, and to the one end of the smoothing capacitor, a third reactor connected to both ends of a series circuit of a secondary winding of the first transformer and a secondary winding of the second transformer, and a control circuit which alternately turns on the first s
    Type: Application
    Filed: July 24, 2008
    Publication date: January 28, 2010
    Applicants: Sanken Electric Co., Ltd., Shimane University
    Inventors: Hideki Asuke, Hideharu Takano, Namoru Tsuruya, Masashi Ochiai, Masayoshi Yamamoto, Takahiro Kawashima, Shigeyuki Funabiki
  • Publication number: 20100012921
    Abstract: A nanowire according to the present invention includes: a nanowire body made of a first material; and a plurality of semiconductor particle made of a second material and being contained in at least a portion of the interior of the nanowire body.
    Type: Application
    Filed: November 29, 2007
    Publication date: January 21, 2010
    Inventors: Takahiro Kawashima, Tohru Saitoh
  • Publication number: 20100001259
    Abstract: A source electrode 105 which is connected to a portion of at least one semiconductor nanostructure 103 among a plurality of semiconductor nanostructures, a drain electrode 106 connected to another portion of the semiconductor nanostructure 103, and a gate electrode 102 capable of controlling electrical conduction of the semiconductor nanostructure 103 are included. The semiconductor nanostructures 103 include a low concentration region 108 having a relatively low doping concentration and a pair of high concentration regions 107 having a higher doping concentration than that of the low concentration region 108 and being connected to both ends of the low concentration region 108.
    Type: Application
    Filed: June 18, 2007
    Publication date: January 7, 2010
    Inventors: Tohru Saitho, Takahiro Kawashima