Abstract: For testing an A/D converter circuit including a pulse delay circuit constituted by a plurality of cascade-connected delay units, and an encoding circuit configured to count the number of the delay units through which the input pulse signal passes within a predetermined measuring time and to output a digital signal representing the counted number, the method includes the steps of setting the A/D converter circuit in a test mode where the measuring time is set at a short test-use sampling period, applying the input pulse signal to each of serial delay blocks each of which is constituted by a predetermined number of the delay units, and determining good and bad of the A/D converter circuit on the basis of digital signals outputted from the encoding circuit representing the numbers of the delay units through which the input pulse signal has passed within each of the serial delay blocks.

Abstract: In an A/D conversion device, each delay unit in a pulse delay circuit has inverters INV of m×n stages (m, n are positive integers), a clock generator has m-delay lines, and each delay line has inverters INV of i×n stages (i=1, 2, . . . , and m). Those delay lines DL1 to DLm output sampling clocks CK1 to CKm. Each of those inverters INV has a same characteristic. In the A/D conversion device, the delay time in each of the delay lines DL1 to DLm is adjusted by the number of the inverters INV. It is thereby possible to provide the m-sampling clocks CK1 to CKm of a different phase ?T with one another, namely whose phases are preciously shifted by ?T with one another.

Abstract: A signal processing unit includes an integrating unit. The integrating unit is composed of a plurality of digital elements and operative to integrate a detection signal over every quarter of one cycle of the detection signal to generate an integration value. The integration values to be generated are represented as S1, S2, S3, S4 . . . . A calculating unit includes a plurality of digital elements and performs addition and subtraction on the generated integration values in accordance with the following equations to calculate an in-phase component and a quadrature-phase component: Ip=S4p?3+S4p?2?S4p?1?S4p Qp=S4p?3?S4p?2?S4p?1+S4p where Ip represents the in-phase component, Qp represents the quadrature-phase component, and p=1, 2, 3 . . . . An amplitude obtaining unit obtains an amplitude of the detection signal based on the in-phase component and the quadrature-phase component.

Abstract: In a positional information detecting device, a tone-burst signal propagating unit causes a tone-burst signal to propagate through a path. The tone-burst signal is composed of a continuous wave train, the continuous wave train including a plurality of cycles of a constant frequency. A detecting unit detects, at a predetermined position in the path, the tone-burst signal propagating through the path every one cycle of the tone-burst signal to measure a propagation delay time based on the detected signal. The propagation delay time represents a period for which the tone-burst signal has propagated through the path. A phase obtaining unit obtains a phase of the detected signal. A positional information obtaining unit obtains positional information associated with the predetermined position based on the measured propagation delay time and the obtained phase of the detected signal.

Abstract: In a radio-controlled device for measuring time, a demodulating unit demodulates the time information from the received electric signal based on amplitude information of the target radio wave. The amplitude information is obtained from in-phase and quadrature-phase components of the target radio wave. A phase calculator calculates phase data associated with a phase of the target radio wave based on the in-phase and quadrature-phase components. A variability calculator calculates a variability of the phase data of the target radio wave relative to a reference phase. The reference phase changes at a constant rate in time according to a frequency error. The frequency error is contained in the reference signal relative to a frequency of the target carrier wave. A reception determining unit determines whether reception of the radio-controlled device is good based on the calculated variability.

Abstract: A TAD (time analog/digital) type of A/D converter has plural series-connected delay units each producing a delay in accordance with the level of a converter input voltage, with a first-stage delay unit receiving a pulse signal at commencement of each A/D conversion sampling interval, and a latch/encoder circuit detecting the total number of delay units traversed by the pulse signal by the end of the sampling interval, to obtain a numeric value expressing the input voltage level. To ensure uniformity of the delays of the delay units, these are formed using transistors of larger size than transistors of other circuits such as the latch/encoder circuit.

Abstract: In a TAD (Time Analog-to-Digital) type of A/D converter in which delay units of a pulse delay circuit successively transfer a pulse signal during each of successive measurement intervals, with each delay unit applying an amount of delay determined by an analog input signal voltage, it is ensured that each new measurement interval begins as soon as the pulse delay circuit has become restored to an initialized condition after the preceding measurement interval. Output values expressing the number of delay units traversed by the pulse signal during a measurement interval are used directly as digital values representing the analog input signal voltage level.

Abstract: An A/D converter has inverting elements and delay elements alternately disposed in series. Each inverting element receives an analog voltage signal as a power source and converts a pulse signal in an inversion operation time depending on the analog voltage signal. Each delay element delays transmission of the pulse signal. The transmission of the pulse signal is started from a starting inverting element at a start time, and a transit position of the pulse signal is detected at a detection time later than the start time by a predetermined time. A digital value indicating a level of the analog voltage signal is determined from the detected transit position of the pulse signal. Because transmission of the pulse signal is delayed by the delay elements, the transit position depending on the analog voltage signal can be correctly detected.

Abstract: In an analog-to-digital converter, a generating unit executes analog-to-digital conversion of a first input signal and a second input signal based on an analog-to-digital conversion characteristic curve to generate first digital data and second digital data respectively corresponding to the first input signal and the second input signal. The input signal has a first level, and the first level is the sum of an offset level and a level of a target analog signal for analog-to-digital conversion. The second input signal has a second level, and the second level is generated by subtracting the offset level from the level of the target analog signal. In the analog-to-digital converter, an obtaining unit obtains difference digital data between the first digital data and the second digital data to output the obtained difference digital data as digital data of the target analog signal.

Abstract: A TAD (time analog/digital) type of A/D converter has plural series-connected delay units each producing a delay in accordance with the level of a converter input voltage, with a first-stage delay unit receiving a pulse signal at commencement of each A/D conversion sampling interval, and a latch/encoder circuit detecting the total number of delay units traversed by the pulse signal by the end of the sampling interval, to obtain a numeric value expressing the input voltage level. To ensure uniformity of the delays of the delay units, these are formed using transistors of larger size than transistors of other circuits such as the latch/encoder circuit.

Abstract: In an A/D conversion device, each delay unit in a pulse delay circuit has inverters INV of m×n stages (m, n are positive integers), a clock generator has m-delay lines, and each delay line has inverters INV of i×n stages (i=1, 2, . . . , and m). Those delay lines DL1 to DLm output sampling clocks CK1 to CKm. Each of those inverters INV has a same characteristic. In the A/D conversion device, the delay time in each of the delay lines DL1 to DLm is adjusted by the number of the inverters INV. It is thereby possible to provide the m-sampling clocks CK1 to CKm of a different phase ?T with one another, namely whose phases are preciously shifted by ?T with one another.

Abstract: An image sensor has plural array blocks B1 to B20 arranged in a two dimensional (2D) arrangement. Each array block has a sub array and a corresponding analogue to digital (A/D) converter for performing an A/D conversion of light signals (or detection signals) output from the sub array. The sub array has plural picture element cells arranged in a 2D arrangement. Each A/D converter has a pulse delay circuit having delay units of plural stages connected in series. Each delay unit delays an input pulse by a delay time corresponding to a level of the light signals received from the sub array. A pulse delay type A/D converter is used as the A/D converter, which outputs the number of the delay units as an A/D conversion data item through which the input pulse passes for a measurement time period.

Abstract: For testing an A/D converter circuit including a pulse delay circuit constituted by a plurality of cascade-connected delay units, and an encoding circuit configured to count the number of the delay units through which the input pulse signal passes within a predetermined measuring time and to output a digital signal representing the counted number, the method includes the steps of setting the A/D converter circuit in a test mode where the measuring time is set at a short test-use sampling period, applying the input pulse signal to each of serial delay blocks each of which is constituted by a predetermined number of the delay units, and determining good and bad of the A/D converter circuit on the basis of digital signals outputted from the encoding circuit representing the numbers of the delay units through which the input pulse signal has passed within each of the serial delay blocks.

Abstract: A radio wave timepiece A and a quadrature detection device for executing a quadrature detecting method are disclosed including a receiving antenna 14 for receiving a carrier wave of a long wave standard radio wave on which time information is multiplexed, a quadrature detection circuit 18 for performing quadrature detection of the carrier wave in response to a reference clock CK1, commonly used for timekeeping by a time counter 8, to obtain an in-phase component I and a quadrature component Q of the carrier wave for obtaining an amplitude AN,m of the carrier wave, and a time correction means 22, 24, 26 for obtaining time information depending on the amplitude of the carrier wave from the quadrature detection circuit 18. The time counter 8 is responsive to time information delivered from the time correction means to correct current time.

Abstract: The present invention is intended to efficiently minimize high-frequency noise stemming from synchronous detection without the necessity of a low-pass filter that requires a large time constant. A vibratory gyroscope includes a synchronous detection unit that detects a sense signal sent from a sensing element using a reference signal synchronous with a monitor signal. In the vibratory gyroscope, an analog moving-average filter that produces a moving average of the detection signal by sampling the detection signal during one cycle of the reference signal is used to remove high-frequency noise components from the detection signal, which is detected to be synchronous with the reference signal, without the necessity of a CR filter that requires a large time constant.

Abstract: An A/D converter has a pulse delay circuit including a plurality of inverting circuits to each of which an analog voltage signal is inputted through a first pair of power supply lines. Each of the inverting circuits has a first logic gate. The A/D converter has a logic circuit having a second logic gate and a second pair of power supply lines, the logic circuit operating based on a power supply voltage. At least one of a first range of a level of the voltage signal and a second range of the power supply voltage is set to prevent a tunneling current from flowing at least one of between the first paired power supply lines and between the second paired power supply lines when at least one of first and second logic gates operates.

Abstract: A method for correcting A/D converted output data which corrects digital data obtained by A/D conversion of an analog signal, comprising forming an at least first order polynomial curve approximating an input/output characteristic curve of A/D conversion in a range of input of the analog signal, setting an ideal input/output characteristic line of A/D conversion, deriving a conversion equation for converting coordinates of a point on the approximation polynomial curve to a point of the ideal input/output characteristic line for the same analog signal value, and using this conversion equation to convert A/D converted digital data so as to correct non-linearity of the output data.

Abstract: An A/D converter for driving a plurality of delay units forming a pulse delay circuit by an analog input signal Vin and digitalizing the number of delay units through which a pulse signal passes in the pulse delay circuit at predetermined timings, provided with a plurality of pulse position digitalizing units used for A/D conversion and inputting delay pulses from the delay units of the pulse delay circuit to the pulse position digitalizing units through an inverter group comprised of inverters with different inversion levels (switching threshold level) by different input timings. The digital data obtained by the pulse position digitalizing units are added by an adder.

Abstract: An A/D converter has a pulse delay circuit including a plurality of inverting circuits to each of which an analog voltage signal is inputted through a first pair of power supply lines. Each of the inverting circuits has a first logic gate. The A/D converter has a logic circuit having a second logic gate and a second pair of power supply lines, the logic circuit operating based on a power supply voltage. At least one of a first range of a level of the voltage signal and a second range of the power supply voltage is set to prevent a tunneling current from flowing at least one of between the first paired power supply lines and between the second paired power supply lines when at least one of first and second logic gates operates.

Abstract: In a synchronous detection method, an input signal is averaged over at least first and second phase ranges of a target carrier wave within each period thereof to obtain at least first and second moving average values of the input signal within the at least first and second phase ranges, respectively. The first phase range corresponds to a positively oscillating phase range of the target carrier wave, and the second phase range corresponds to a negatively oscillating phase range thereof. A difference between the first and second moving averages is calculated as a detection result of the target carrier wave.