Abstract: An analog-to-digital conversion device is provided that uses pulse delay circuits to convert an input voltage into numerical data and offers a high resolution in analog-to-digital conversion or a high analog-to-digital conversion rate. The analog-to-digital conversion device includes an analog-to-digital conversion unit having a pulse delay circuit composed of a plurality of delay units. The delay units are driven with a voltage produced by amplifying or shifting an input voltage. The number of delay units through which a pulse signal has passed during a predetermined sampling cycle is adopted as a digitized value of the input voltage. Herein, delay units constituting another pulse delay circuit are driven with a voltage produced by inversely amplifying or shifting the input voltage.

Abstract: An A/D converter for driving a plurality of delay units forming a pulse delay circuit by an analog input signal Vin and digitalizing the number of delay units through which a pulse signal passes in the pulse delay circuit at predetermined timings, provided with a plurality of pulse position digitalizing units used for A/D conversion and inputting delay pulses from the delay units of the pulse delay circuit to the pulse position digitalizing units through an inverter group comprised of inverters with different inversion levels (switching threshold level) by different input timings. The digital data obtained by the pulse position digitalizing units are added by an adder.

Abstract: A method for correcting A/D converted output data which corrects digital data obtained by A/D conversion of an analog signal, comprising forming an at least first order polynomial curve approximating an input/output characteristic curve of A/D conversion in a range of input of the analog signal, setting an ideal input/output characteristic line of A/D conversion, deriving a conversion equation for converting coordinates of a point on the approximation polynomial curve to a point of the ideal input/output characteristic line for the same analog signal value, and using this conversion equation to convert A/D converted digital data so as to correct non-linearity of the output data.

Abstract: In a device for analog-to-digital converting an input signal, the input signal is applied to a plurality of delay units constituting a pulse delay circuit in order to change a delay time to be given by the delay units. The number of delay units through which a pulse signal has passed during one period of sampling clocks is numerically expressed. The A/D conversion device has a plurality of pulse position numerizing units that is used for A/D conversion. Sampling clocks of which the phases are different from one another are applied to the respective pulse position numerizing units. An adder summates numerical data items produced by the respective pulse position numerizing units so as to generate final numerical data representing a result of A/D conversion.

Abstract: In a shift clock signal generating apparatus, a delay line includes a plurality of unit delay elements connected in cascade. A reference clock signal propagates in the delay line while being successively delayed by the unit delay elements. Switches have first ends connected with output terminals of the unit delay elements respectively, and second ends connected with a shift clock signal output path. When specified one among the switches is in its on position, a delayed clock signal which results from delaying the reference clock signal by a prescribed time interval is transmitted via the specified switch to the shift clock signal output path as a shift clock signal. The specified one among the switches is determined on the basis of data representing a phase difference of the shift clock signal from the reference clock signal. The specified switch is set in its on position.

Abstract: In a shift clock signal generating apparatus, a delay line includes a plurality of unit delay elements connected in cascade. A reference clock signal propagates in the delay line while being successively delayed by the unit delay elements. Switches have first ends connected with output terminals of the unit delay elements respectively, and second ends connected with a shift clock signal output path. When specified one among the switches is in its on position, a delayed clock signal which results from delaying the reference clock signal by a prescribed time interval is transmitted via the specified switch to the shift clock signal output path as a shift clock signal. The specified one among the switches is determined on the basis of data representing a phase difference of the shift clock signal from the reference clock signal. The specified switch is set in its on position.

Abstract: A system working to detect a reciprocating motion of an object such as a scanner mirror of an optical scanner. The system is designed to compensate for an error which is concluded in an amplified sensor signal used to determine a reference position of the scanner mirror and which is sensitive to a change in environmental condition of use such as a change in ambient temperature. The system also works to monitor a change in amplitude of swing of the scanner mirror accurately to keep it constant.

Abstract: In an A/D conversion apparatus comprising an A/D converter (4) and a digital moving average filter (6) for removing high-frequency signal components, there is provided an analog moving average filter (2) at a first stage. A sampling frequency of the filters (6 and 2) is set to fsd=n×fsa (where n is a positive integer of 1, 2, ---). As a result, it becomes possible to superimpose an unnecessary signal passing area that appears at every frequency of n times the sampling frequency fsd in the filter (6), on an area of infinite attenuation that appears at every frequency of n times the sampling frequency fsa in the filter (2). In the apparatus as a whole, it becomes possible to efficiently attenuate unnecessary high-frequency signal components. It is also possible to obtain a similar effect when a time A/D converter is used in place of the analog moving average filter (2) and the A/D converter (4).

Abstract: In a device for analog-to-digital converting an input signal, the input signal is applied to a plurality of delay units constituting a pulse delay circuit in order to change a delay time to be given by the delay units. The number of delay units through which a pulse signal has passed during one period of sampling clocks is numerically expressed. The A/D conversion device has a plurality of pulse position numerizing units that is used for A/D conversion. Sampling clocks of which the phases are different from one another are applied to the respective pulse position numerizing units. An adder summates numerical data items produced by the respective pulse position numerizing units so as to generate final numerical data representing a result of A/D conversion.

Abstract: In a shift clock signal generating apparatus, a delay line includes a plurality of unit delay elements connected in cascade. A reference clock signal propagates in the delay line while being successively delayed by the unit delay elements. Switches have first ends connected with output terminals of the unit delay elements respectively, and second ends connected with a shift clock signal output path. When specified one among the switches is in its on position, a delayed clock signal which results from delaying the reference clock signal by a prescribed time interval is transmitted via the specified switch to the shift clock signal output path as a shift clock signal. The specified one among the switches is determined on the basis of data representing a phase difference of the shift clock signal from the reference clock signal. The specified switch is set in its on position.

Abstract: A coarse measuring circuit measures an approximate measurement object time DU based on a first reference clock CK10. The approximate measurement object time represents a duration from a measurement start time to an input time of measurement object pulse PBr. A fine measuring circuit, cooperating with the coarse measuring circuit and using a shorter reference time, measures a time difference between a change point of the first reference clock CK10 and the input time of measurement object pulse PBr as a correction time DD of the approximate measurement object time DU, thereby obtaining a precise measurement objet time DT.

Abstract: The present invention is intended to efficiently minimize high-frequency noise stemming from synchronous detection without the necessity of a low-pass filter that requires a large time constant. A vibratory gyroscope includes a synchronous detection unit that detects a sense signal sent from a sensing element using a reference signal synchronous with a monitor signal. In the vibratory gyroscope, an analog moving-average filter that produces a moving average of the detection signal by sampling the detection signal during one cycle of the reference signal is used to remove high-frequency noise components from the detection signal, which is detected to be synchronous with the reference signal, without the necessity of a CR filter that requires a large time constant.

Abstract: In an A/D conversion apparatus comprising an A/D converter (4) and a digital moving average filter (6) for removing high-frequency signal components, there is provided an analog moving average filter (2) at a first stage. A sampling frequency of the filters (6 and 2) is set to fsd =n x fsa (where n is a positive integer of 1, 2, ---). As a result, it becomes possible to superimpose an unnecessary signal passing area that appears at every frequency of n times the sampling frequency fsd in the filter (6), on an area of infinite attenuation that appears at every frequency of n times the sampling frequency fsa in the filter (2). In the apparatus as a whole, it becomes possible to efficiently attenuate unnecessary high-frequency signal components. It is also possible to obtain a similar effect when a time A/D converter is used in place of the analog moving average filter (2) and the A/D converter (4).

Abstract: An analog input signal is inputted into a pulse delay circuit including a series combination of delay units. The analog input signal controls signal delay times provided by the respective delay units. A pulse signal is inputted into the pulse delay circuit. The pulse signal is transmitted in the pulse delay circuit while being sequentially delayed by the delay units. Detection is made as to a number of ones among the delay units through which the pulse signal has passed during a setting time from a moment at which the pulse signal is inputted into the pulse delay circuit. Information representative of a level of the analog input signal is generated in response to the detected number.

Abstract: An object of the present invention is to provide an analog-to-digital conversion device that uses pulse delay circuits to convert an input voltage into numerical data and that offers a high resolution in analog-to-digital conversion or a high analog-to-digital conversion rate. The analog-to-digital conversion device includes an analog-to-digital conversion unit having a pulse delay circuit composed of a plurality of delay units. The delay units are driven with a voltage produced by amplifying or shifting an input voltage. The number of delay units through which a pulse signal has passed during a predetermined sampling cycle is adopted as a digitized value of the input voltage. Herein, delay units constituting another pulse delay circuit are driven with a voltage produced by inversely amplifying or shifting the input voltage.

Abstract: A system working to detect a reciprocating motion of an object such as a scanner mirror of an optical scanner. The system is designed to compensate for an error which is concluded in an amplified sensor signal used to determine a reference position of the scanner mirror and which is sensitive to a change in environmental condition of use such as a change in ambient temperature. The system also works to monitor a change in amplitude of swing of the scanner mirror accurately to keep it constant.

Abstract: An analog input voltage signal to be A/D-converted is supplied to a ring gate delay circuit including inverting circuits connected in series in a ring as a supply voltage thereto. The interval for which a pulse circulates the ring varies with the analog input voltage signal. The number of times circulation of the pulse and the position of the pulse for a predetermined interval are detected by a counter to provide upper bits and by a pulse position detector to provide lower bits of A/D conversion result of the analog input voltage signal, respectively. The counter and the pulse position detector are included in a coding process block which is driven by a constant voltage which is different from the analog input voltage signal to the ring gate delay circuit.

Abstract: In a shift clock signal generating apparatus, a delay line includes a plurality of unit delay elements connected in cascade. A reference clock signal propagates in the delay line while being successively delayed by the unit delay elements. Switches have first ends connected with output terminals of the unit delay elements respectively, and second ends connected with a shift clock signal output path. When specified one among the switches is in its on position, a delayed clock signal which results from delaying the reference clock signal by a prescribed time interval is transmitted via the specified switch to the shift clock signal output path as a shift clock signal. The specified one among the switches is determined on the basis of data representing a phase difference of the shift clock signal from the reference clock signal. The specified switch is set in its on position.

Abstract: An analog input signal is inputted into a pulse delay circuit including a series combination of delay units. The analog input signal controls signal delay times provided by the respective delay units. A pulse signal is inputted into the pulse delay circuit. The pulse signal is transmitted in the pulse delay circuit while being sequentially delayed by the delay units. Detection is made as to a number of ones among the delay units through which the pulse signal has passed during a setting time from a moment at which the pulse signal is inputted into the pulse delay circuit. Information representative of a level of the analog input signal is generated in response to the detected number.

Abstract: A coarse measuring circuit measures an approximate measurement object time DU based on a first reference clock CK10. The approximate measurement object time represents a duration from a measurement start time to an input time of measurement object pulse PBr. A fine measuring circuit, cooperating with the coarse measuring circuit and using a shorter reference time, measures a time difference between a change point of the first reference clock CK10 and the input time of measurement object pulse PBr as a correction time DD of the approximate measurement object time DU, thereby obtaining a precise measurement objet time DT.