Patents by Inventor Takashi Hashimoto

Takashi Hashimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210317465
    Abstract: Four genes, A622, NBB1, PMT, and QPT, can be influenced for increasing nicotinic alkaloid levels in Nicotiana plants, as well as for synthesizing nicotinic alkaloids in non-nicotine producing plants and cells. In particular, overexpressing one or more of A622, NBB1, PMT, and QPT may be used to increase nicotine and nicotinic alkaloid levels in tobacco plants. Non-nicotine producing cells can be engineered to produce nicotine and related compounds by overexpressing A622 and NBB1.
    Type: Application
    Filed: January 4, 2021
    Publication date: October 14, 2021
    Applicant: 22nd Century Limited, LLC
    Inventors: Takashi HASHIMOTO, Masataka KAJIKAWA
  • Publication number: 20210320366
    Abstract: A battery pack includes a battery, a storage box, and a high voltage component. The storage box stores the battery, and includes a load transmitter configured to transmit a load applied upon occurrence of a collision. The high voltage component is configured to be electrically coupled to the battery, structurally coupled to the load transmitter, and disposed forwardly of the battery within the storage box.
    Type: Application
    Filed: April 2, 2021
    Publication date: October 14, 2021
    Applicant: SUBARU CORPORATION
    Inventor: Takashi HASHIMOTO
  • Patent number: 11145744
    Abstract: In a semiconductor device including a nonvolatile memory, information of a memory transistor of an unselected bit is accidentally erased during information write operation. A well region is provided in a memory region of a bulk region defined in a SOI substrate. A memory transistor having an LDD region and a diffusion layer is provided in the well region. A raised epitaxial layer is provided on the surface of the well region. The LDD region is provided from a portion of the well region located directly below a sidewall surface of a gate electrode to a portion of the well region located directly below the raised epitaxial layer. The diffusion layer is provided in the raised epitaxial layer.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: October 12, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinichiro Abe, Takashi Hashimoto, Hideaki Yamakoshi, Yuto Omizu
  • Publication number: 20210308794
    Abstract: An additive manufacturing apparatus includes a laser oscillator that is a beam source that outputs a beam, and a rotary motor that is a driving unit that changes the relative positions of a material fed from a wire spool that is a supply source of a wire that is the material and an object to be machined. The driving unit is capable of performing first driving for feeding the material from the supply source toward the object to be machined and second driving for pulling back the fed material to the supply source, and switches from the first driving to the second driving on the basis of a machining program.
    Type: Application
    Filed: October 24, 2018
    Publication date: October 7, 2021
    Applicant: Mitsubishi Electric Corporation
    Inventors: Satoshi HATTORI, Takashi HASHIMOTO, Nobuyuki SUMI
  • Patent number: 11134260
    Abstract: An encoder that encodes a picture to generate a coded stream includes: circuitry and a memory coupled to the circuitry. The circuitry performs, using the memory: generating a prediction image of a current block included in a current picture by referring to a first region included in a reference picture different from the current picture; operating a bi-directional optical flow process to correct the prediction image by referring to a second region included in the first region, and not operating the bi-directional optical flow process in response to the second region not being included in the first region; and encoding the current block based on the prediction image.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: September 28, 2021
    Assignee: Panasonic Intellectual Property Corporation of America
    Inventors: Takashi Hashimoto, Kiyofumi Abe, Tadamasa Toma, Takahiro Nishi, Ryuichi Kanoh
  • Publication number: 20210297692
    Abstract: An encoder includes circuitry and memory. Using the memory, the circuitry, in inter prediction processing: derives a first motion vector of a current block to be processed, using a motion vector of a previous block which has been previously processed; derives a second motion vector of the current block by performing motion estimation in the vicinity of the first motion vector; and generates a prediction image of the current block by performing motion compensation using the second motion vector.
    Type: Application
    Filed: June 8, 2021
    Publication date: September 23, 2021
    Inventors: Kiyofumi ABE, Takahiro NISHI, Tadamasa TOMA, Ryuichi KANOH, Takashi HASHIMOTO
  • Publication number: 20210281758
    Abstract: A shake correction control device includes an acquisition unit that acquires imaging information for selecting mechanical correction of mechanically performing shake correction of a subject image or electronic correction of electronically performing the shake correction of the subject image, and a shake correction control unit. The shake correction control unit performs a first control for performing a switching control from the mechanical correction to the electronic correction by synchronizing shake correction operations of the mechanical correction and the electronic correction and a second control, different from the first control, for performing a switching control from the electronic correction to the mechanical correction based on the imaging information acquired by the acquisition unit.
    Type: Application
    Filed: May 25, 2021
    Publication date: September 9, 2021
    Applicant: FUJIFILM Corporation
    Inventors: Tomonori MASUDA, Masahiko SUGIMOTO, Yi PAN, Takashi HASHIMOTO, Tetsuya FUJIKAWA, Yasunobu KISHINE
  • Patent number: 11109617
    Abstract: Two genes, A622 and NBB1, can be influenced to achieve a decrease of nicotinic alkaloid levels in plants. In particular, suppression of one or both of A622 and NBB1 may be used to decrease nicotine in tobacco plants.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: September 7, 2021
    Assignee: 22nd Century Limited, LLC
    Inventors: Takashi Hashimoto, Akira Kato
  • Publication number: 20210274099
    Abstract: A shake correction control device includes an acquisition unit and an operation control unit. The acquisition unit acquires, for each predetermined time, a related amount related to an operation recommendation condition under which an operation of a mechanical correction unit which corrects a shake of a subject image by mechanically moving at least one of a correction optical system or an imaging element is recommended. The operation control unit controls the operation of the mechanical correction unit and an operation of an electronic correction unit which corrects the shake by performing image processing on an image obtained by imaging performed by the imaging element.
    Type: Application
    Filed: May 18, 2021
    Publication date: September 2, 2021
    Applicant: FUJIFILM Corporation
    Inventors: Yi PAN, Masahiko SUGIMOTO, Tomonori MASUDA, Takashi HASHIMOTO, Tetsuya FUJIKAWA, Yasunobu KISHINE
  • Publication number: 20210274098
    Abstract: A shake correction control device includes an acquisition unit and an operation control unit. The acquisition unit acquires, for each predetermined time, a related amount related to each of a first operation recommendation condition under which an operation of a mechanical correction unit that corrects a shake of a subject image by mechanically moving at least one of a correction optical system or an imaging element is recommended, and a second operation recommendation condition under which an operation of an electronic correction unit that corrects the shake by performing image processing on an image obtained by imaging performed by the imaging element is recommended.
    Type: Application
    Filed: May 18, 2021
    Publication date: September 2, 2021
    Applicant: FUJIFILM Corporation
    Inventors: Masahiko SUGIMOTO, Tomonori MASUDA, Yi PAN, Takashi HASHIMOTO, Tetsuya FUJIKAWA, Yasunobu KISHINE
  • Patent number: 11064216
    Abstract: An encoder includes circuitry and memory. Using the memory, the circuitry, in inter prediction processing: derives a first motion vector of a current block to be processed, using a motion vector of a previous block which has been previously processed; derives a second motion vector of the current block by performing motion estimation in the vicinity of the first motion vector; and generates a prediction image of the current block by performing motion compensation using the second motion vector.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: July 13, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Kiyofumi Abe, Takahiro Nishi, Tadamasa Toma, Ryuichi Kanoh, Takashi Hashimoto
  • Patent number: 11049869
    Abstract: A MONOS transistor as a first transistor can have improved reliability and a change in channel-width dependence of the property of a second transistor can be suppressed. The semiconductor device according to one embodiment includes a semiconductor substrate having first and second regions on the first main surface, an insulating film on the second region, a semiconductor layer on the insulating film, a memory transistor region in the first region, a first transistor region in the second main surface of the semiconductor layer, a first element isolation film surrounding the memory transistor region, and a second element isolation film surrounding the first transistor region. A first recess depth between the bottom of the first recess and the first main surface in the memory transistor region is larger than a second recess depth between the bottom of a second recess and the second main surface in the first transistor region.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: June 29, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hideaki Yamakoshi, Shinichiro Abe, Takashi Hashimoto, Yuto Omizu
  • Publication number: 20210174630
    Abstract: An automatic vending machine includes: a belt conveyor constituting a part of a column configured to store a product, the belt conveyor being able to convey the stored product along the column, and a controller configured to control an operation of the belt conveyor. The controller acquires an amount of movement of a belt of the belt conveyor moving to convey the product. The controller calculates the number of products stored in the column, based on the acquired amount of movement of the belt.
    Type: Application
    Filed: October 25, 2018
    Publication date: June 10, 2021
    Inventors: TAKAYA IBE, TAKASHI HASHIMOTO
  • Patent number: 11017971
    Abstract: A differential electrical protection device D including N?1 phase conductors, each phase conductor including, between an input, or upper, connection land and an output, or lower, connection land, a portion able to pass through a torus and a portion able to pass through a current measurement and supply sensor, the input connection lands being situated in a first plane P1, and the output connection lands extending in a second plane P2, in that the supply and measurement sensors of the N?1 phase conductors are each positioned in the space situated between the two planes P1,P2, and wherein it includes an additional phase conductor including an input connection land and an output connection land, a portion able to pass through the torus and a portion able to pass through an additional measurement sensor only measuring the current, this additional measurement sensor being of small size and being positioned directly above the torus in such a way that the assembly formed by the torus and the additional sensor is situ
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: May 25, 2021
    Assignees: Schneider Electric Industries SAS, Fuji Electric FA Components & Systems Co., Ltd
    Inventors: Jean-Pierre Nereau, Yutaka Sato, Takashi Hashimoto, Yohei Hosooka
  • Publication number: 20210151609
    Abstract: A semiconductor device includes a memory cell which is configured of a FinFET having a split-gate type MONOS structure, the FinFET has a plurality of source regions formed in a plurality of fins, and the plurality of source regions are commonly connected by a source line contact. Further, the FinFET has a plurality of drain regions formed in the plurality of fins, the plurality of drain regions are commonly connected by a bit line contact, and the FinFET constitutes a memory cell of 1 bit.
    Type: Application
    Filed: October 29, 2020
    Publication date: May 20, 2021
    Inventors: Digh HISAMOTO, Yoshiyuki KAWASHIMA, Takashi HASHIMOTO
  • Publication number: 20210152842
    Abstract: A decoder that decodes a current block using a motion vector includes: a processor; and memory. Using the memory, the processor: derives a first candidate vector from one or more candidate vectors of one or more neighboring blocks that neighbor the current block; determines, in a first reference picture for the current block, a first adjacent region that includes a position indicated by the first candidate vector; calculates evaluation values of a plurality of candidate regions included in the first adjacent region; and determines a first motion vector of the current block, based on a first candidate region having a smallest evaluation value among the evaluation values. The first adjacent region is included in a first motion estimation region determined based on the position indicated by the first candidate vector.
    Type: Application
    Filed: December 22, 2020
    Publication date: May 20, 2021
    Inventors: Takashi HASHIMOTO, Takahiro NISHI, Tadamasa TOMA, Kiyofumi ABE, Ryuichi KANOH
  • Publication number: 20210143260
    Abstract: A semiconductor device has a split-gate type MONOS structure using a FinFET, and it includes a source and a drain each formed of an n-type impurity diffusion layer, a first channel forming layer which is formed under a control gate and is formed of a semiconductor layer doped with a p-type impurity, and a second channel forming layer which is formed under a memory gate and is formed of a semiconductor layer doped with an n-type impurity. Further, the semiconductor device includes a p-type semiconductor layer which is formed under the second channel forming layer and has an impurity concentration higher than an impurity concentration of a semiconductor substrate.
    Type: Application
    Filed: October 29, 2020
    Publication date: May 13, 2021
    Inventors: Digh HISAMOTO, Yoshiyuki KAWASHIMA, Takashi HASHIMOTO
  • Publication number: 20210127114
    Abstract: An encoder includes memory and circuitry accessible to the memory. The circuitry accessible to the memory: switches whether or not to apply arithmetic encoding to a binary data string in which image information has been binarized; binarizes frequency transform coefficient information according to different binarization formats between when arithmetic encoding is applied to the binary data string and when arithmetic encoding is not applied to the binary data string; and binarizes a part or the entirety of prediction parameter information according to a binarization format which is common between when arithmetic encoding is applied to the binary data string and when arithmetic encoding is not applied to the binary data string.
    Type: Application
    Filed: January 5, 2021
    Publication date: April 29, 2021
    Inventors: Kiyofumi ABE, Takahiro NISHI, Takashi HASHIMOTO, Tadamasa TOMA
  • Patent number: 10978385
    Abstract: This invention is to improve a performance of a semiconductor device. The semiconductor device includes a semiconductor substrate, a p-type well region formed in the semiconductor substrate, a first insulating layer formed over the p-type well region, a semiconductor layer formed over the first insulating layer, a second insulating layer formed over the semiconductor layer, and a conductor layer formed over the second insulating layer. A first capacitive element is comprised of the semiconductor layer, the second insulating layer, and the conductor layer, while a second capacitive element is comprised of the p-type well region, the first insulating layer, and the semiconductor layer, in which each of the semiconductor substrate and the semiconductor layer includes a single crystal silicon layer.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: April 13, 2021
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshiyuki Kawashima, Takashi Hashimoto
  • Patent number: 10951896
    Abstract: An encoder includes memory and circuitry accessible to the memory. The circuitry accessible to the memory: switches whether or not to apply arithmetic encoding to a binary data string in which image information has been binarized; binarizes frequency transform coefficient information according to different binarization formats between when arithmetic encoding is applied to the binary data string and when arithmetic encoding is not applied to the binary data string; and binarizes a part or the entirety of prediction parameter information according to a binarization format which is common between when arithmetic encoding is applied to the binary data string and when arithmetic encoding is not applied to the binary data string.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: March 16, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Kiyofumi Abe, Takahiro Nishi, Takashi Hashimoto, Tadamasa Toma