Abstract: A virtual memory control multiprocessor system has a plurality of processors each having a translation lookaside buffer (TLB). A purge request source processor commonly supplies a purge request signal to other processors so as to cause them to perform TLB purge operations. A purge end signal sent back from other processors is stored in flip-flops in the source processor in units of processors. The source processor detects the end of TLB purge operations of all processors, in accordance with the statuses of the flip-flops.

Abstract: An information processing system having a main memory unit, an arithmetic control unit, and a plurality of input/output units, is comprised of a first bus, which is bidirectional, commonly connecting the main memory unit, the arithmetic control unit, and at least one input/output unit, a bus controller for controlling data transfer between two units connecting to the first bus, a second bus, which is also bidirectional, commonly connecting to the arithmetic control unit with at least another input/output unit, and a bus control means which is provided in the arithmetic control unit and controls data transfer between two units connecting to the second bus. The information processing system uses various units connecting to the first and second buses in time sharing and multiplexing mode.

Abstract: A synthetic resin laminate composed of a supporting plate having protrusions and a foamed sheet having fine through-holes and fixed to the protrusions is produced by placing a foamed sheet extruded on the protrusions of a supporting plate heated to a temperature suitable for fusion-fixing and applying a draft to the supporting plate at a speed more than, but not exceeding 5 times the speed of the foamed sheet.