Patents by Inventor Takashi Horii

Takashi Horii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4807193
    Abstract: A one-transistor one-capacitor type semiconductor memory device having a detection circuit for detecting the electric potential of a word line, to determine an appropriate timing for driving a sense amplifier, thereby improving the speed of memory operations.
    Type: Grant
    Filed: February 25, 1987
    Date of Patent: February 21, 1989
    Assignee: Fujitsu Limited
    Inventors: Yoshihiro Takemae, Takeo Takematsu, Kimiaki Sato, Takashi Horii, Nobumi Kodama, Makoto Yanagisawa, Yasuhiro Takada
  • Patent number: 4752914
    Abstract: A semiconductor integrated circuit including a memory unit for storing address information of a failed circuit portion and for replacing the failed circuit portion by a redundant circuit portion. The semiconductor integrated circuit provides a comparison unit for detecting coincidence between data read from the memory unit and a received input address. Data produced from the comparison by the comparison unit is delivered through an external connection terminal.
    Type: Grant
    Filed: May 30, 1985
    Date of Patent: June 21, 1988
    Assignee: Fujitsu Limited
    Inventors: Masao Nakano, Yoshihiro Takemae, Tomio Nakano, Takeo Tatematsu, Junji Ogawa, Takashi Horii, Yasuhiro Fujii, Kimiaki Sato, Norihisa Tsuge, Itaru Tsuge, Sachie Tsuge
  • Patent number: 4707806
    Abstract: A device connected between first and second voltage feed lines includes an information storing circuit having a fuse for storing information by blowing or not blowing the fuse, a voltage level conversion circuit connected to at least one of the first and second voltage feed lines and outputting a voltage lower than a voltage between the first and second voltage feed lines to the information storing circuit, and a circuit connected between the first and second voltage feed lines, for outputting a detection signal in response to a voltage value at the fuse in the information storing circuit to which the voltage is applied from the voltage level conversion circuit and which voltage value is varied with the blown or unblown state of the fuse.
    Type: Grant
    Filed: March 15, 1985
    Date of Patent: November 17, 1987
    Assignee: Fujitsu Limited
    Inventors: Yoshihiro Takemae, Tomio Nakano, Takeo Tatematsu, Junji Ogawa, Takashi Horii, Yasuhiro Fujii, Masao Nakano, Norihisa Tsuge, deceased
  • Patent number: 4592025
    Abstract: A circuit for storing information by blown and unblown fuses has at least two fuses per bit and an information output circuit. The information output circuit discriminates between the state in which all the fuses are unblown and the state in which at least one of the fuses is blown, and provides an output in accordance with the result of the discrimination as stored information.
    Type: Grant
    Filed: April 10, 1984
    Date of Patent: May 27, 1986
    Assignee: Fujitsu Limited
    Inventors: Yoshihiro Takemae, Junji Ogawa, Yasuhiro Fujii, Tomio Nakano, Takeo Tatematsu, Takashi Horii, Masao Nakano, Norihisa Tsuge, deceased
  • Patent number: 4583179
    Abstract: A semiconductor integrated circuit which includes therein at least one inspection circuit for inspecting a voltage level produced at an internal node to be inspected. The inspection circuit has at least a control signal input portion connected to the internal node to be inspected and an input part connected to an external input/output pin. The inspection circuit includes a series-connected transistor and diode connected between a power source and the input portion, a capacitor connected between a gate of the transistor and the input portion, and a transfer gate transistor connected between the control signal input portion and the gate of the transistor. The inspection circuit discriminates the level at the internal node according to a flow or nonflow of a current, via the external input/output pin, when a particular signal having a voltage level higher than the power source level is supplied to the external input/output pin.
    Type: Grant
    Filed: December 29, 1982
    Date of Patent: April 15, 1986
    Assignee: Fujitsu Limited
    Inventors: Takashi Horii, Tomio Nakano, Masao Nakano, Norihisa Tsuge, Junji Ogawa
  • Patent number: 4578781
    Abstract: An MIS transistor circuit which is operated alternately in a reset state and in an active state, comprises a voltage holding circuit for holding a power supply voltage applied in each reset state so as to provide a clamped voltage. The clamped voltage is applied during each active state to the desired nodes of the MIS transistor circuit as an actual power supply voltage, whereby error operation due to voltage fluctuation of the power supply voltage is prevented.
    Type: Grant
    Filed: August 31, 1982
    Date of Patent: March 25, 1986
    Assignee: Fujitsu Limited
    Inventors: Junji Ogawa, Tomio Nakano, Masao Nakano, Norihisa Tsuge, Takashi Horii
  • Patent number: 4454076
    Abstract: Disclosed herein is a variable venturi carburetor including at least one pressure controlling port provided at the lower peripheral portion of the suction piston and adapted to face to a mixing chamber defined directly downstream of the venturi portion. The pressure controlling port is located at such a position as to communicate with the suction chamber and an atmospheric pressure chamber during middle and high intake air flowing stages as the suction piston reciprocates transversely with respect to the venturi portion, and to communicate with the suction chamber and the mixing chamber during low intake air flowing stage.
    Type: Grant
    Filed: December 30, 1982
    Date of Patent: June 12, 1984
    Assignee: Aisan Kogyo Kabushiki Kaisha
    Inventors: Satomi Wada, Masanori Senda, Takashi Horii, Yozo Ota