Patents by Inventor Takashi Ishida
Takashi Ishida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11251193Abstract: A semiconductor memory device includes a substrate, gate electrodes arranged in a thickness direction of the substrate, first and second semiconductor layers, a gate insulating film, and a first contact. The first semiconductor layer extends in the thickness direction and faces the gate electrodes. The gate insulating film is between the gate electrodes and the first semiconductor layer. The second semiconductor layer is between the substrate and the gate electrodes and connected to a side surface of the first semiconductor layer in a surface direction. The first contact extends in the thickness direction and electrically connected to the second semiconductor layer. The second semiconductor layer includes a first region in contact with the side surface of the first semiconductor layer and containing P-type impurities, and a first contact region electrically connected to the first contact and having a higher concentration of N-type impurities than the first region.Type: GrantFiled: September 3, 2019Date of Patent: February 15, 2022Assignee: TOSHIBA MEMORY CORPORATIONInventors: Ken Komiya, Takashi Ishida, Hiroshi Kanno
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Publication number: 20220015996Abstract: A water-type or oil-in-water type cosmetic provided with a watery feeling in use and high ultraviolet protection ability. The water-type or oil-in-water-type cosmetic according to the present invention is characterized by containing (A) a porous spherical powder having an average particle size of 1 to 4 ?m and an oil absorption rate of 160 ml/100 g or lower; and (B) an ultraviolet absorption agent.Type: ApplicationFiled: November 18, 2019Publication date: January 20, 2022Applicant: Shiseido Company, Ltd.Inventors: Yurika WATANABE, Takashi ISHIDA, Kazuhiro YAMAGUCHI
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Publication number: 20210391011Abstract: A semiconductor storage device includes a plurality of memory cell transistors, a first wiring electrically connected to the plurality of memory cell transistors, and an erasing circuitry. The erasing circuitry is configured to erase data stored in the memory cell transistors by applying a first voltage to the first wiring, and apply the first voltage such that the first voltage rises to a first value, then falls from the first value to a second value, and is then maintained at the second value.Type: ApplicationFiled: March 3, 2021Publication date: December 16, 2021Inventors: Takashi ISHIDA, Hiroshi KANNO
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Patent number: 11142497Abstract: An object of the present invention is to provide a novel plant growth inhibiting agent and a plant growth inhibiting method using the same. The plant growth inhibiting agent of the present invention comprises, as an active ingredient, a compound represented by the following formula (I?) and/or a salt thereof. In the formula (I?), R1a represents a substituted or unsubstituted C1 to C20 alkyl group, a substituted or unsubstituted C6 to C14 aryl group, a substituted or unsubstituted C3 to C13 heteroaryl group, or the like; R2 represents a substituted or unsubstituted C1 to C20 alkylene group, a substituted or unsubstituted C6 to C14 arylene group, or the like; R3a represents OH, a substituted or unsubstituted C1 to C6 alkoxy group, or the like; X represents an oxygen atom; Y represents a substituent; q represents any integer of 0 to 3; n represents 0 or 1; and m represents 0 or 1.Type: GrantFiled: February 6, 2018Date of Patent: October 12, 2021Assignees: National University Corporation Kumamoto University, Nippon Soda Co., Ltd.Inventors: Hayato Ishikawa, Tokio Tani, Shinichiro Sawa, Takashi Ishida, Yusuke Fukushima, Jun Inagaki
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Publication number: 20210284434Abstract: An extraction bag 1A includes a bag main body 3 formed of a water permeable filter sheet 2, a thin plate-like member 10 provided on an outer surface of the bag main body 3, and an extraction material filled in the bag main body 3. The bag main body 3 has a first surface 3A and a second surface 3B opposed to each other, and an upper side 4a corresponding to edges thereof. The thin plate-like member 10 includes a first member 10A on the first surface 3A of the bag main body, and a second member 10B on the second surface 3B of the bag main body, and these 10A and 10B are continuous with each other via a first horizontal folding line Lh1 extending along the upper side 4a.Type: ApplicationFiled: March 11, 2020Publication date: September 16, 2021Applicant: OHKI Co., Ltd.Inventors: Takashi ISHIDA, Mitsunori SAITOH
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Publication number: 20210276950Abstract: An object of the present invention is to provide a novel plant growth inhibiting agent and a plant growth inhibiting method using the same. The plant growth inhibiting agent of the present invention comprises, as an active ingredient, a compound represented by the following formula (I?) and/or a salt thereof. In the formula (I?), R1a represents a substituted or unsubstituted C1 to C20 alkyl group, a substituted or unsubstituted C6 to C14 aryl group, a substituted or unsubstituted C3 to C13 heteroaryl group, or the like; R2 represents a substituted or unsubstituted C1 to C20 alkylene group, a substituted or unsubstituted C6 to C14 arylene group, or the like; R3a represents OH, a substituted or unsubstituted C1 to C6 alkoxy group, or the like; X represents an oxygen atom; Y represents a substituent; q represents any integer of 0 to 3; n represents 0 or 1; and m represents 0 or 1.Type: ApplicationFiled: February 6, 2018Publication date: September 9, 2021Applicants: NATIONAL UNIVERSITY CORPORATION KUMAMOTO UNIVERSITY, Nippon Soda Co., Ltd.Inventors: Hayato ISHIKAWA, Tokio TANI, Shinichiro SAWA, Takashi ISHIDA, Yusuke FUKUSHIMA, Jun INAGAKI
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Publication number: 20210273055Abstract: A semiconductor storage device according to the present embodiment includes a first semiconductor layer containing impurities. A stacked body is provided above the first semiconductor layer and includes insulating layers and conductive layers that are alternately stacked. A semiconductor body penetrates through the stacked body in a stacking direction to reach the first semiconductor layer and includes a lower region on a side of the first semiconductor layer and an upper region positioned above the lower region. A charge accumulation part is provided between the semiconductor bodies and the conductive layers. An impurity concentration of the lower region of the semiconductor body is higher than that of the first semiconductor layer.Type: ApplicationFiled: September 14, 2020Publication date: September 2, 2021Inventors: Naomi YANAI, Yasuhito YOSHIMIZU, Takashi ISHIDA
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Patent number: 11075122Abstract: A semiconductor device according to an embodiment includes: a semiconductor substrate including a first surface, a first contact part provided at a deeper level than the first surface, and a second contact part protruding up to a higher level than the first surface from the first contact part; a stacked body in which insulating layers and electrode layers are alternately stacked on the first surface; and a semiconductor film extending, on the second contact part, in the stacked body in a first direction perpendicular to the first surface. At an interface between the first contact part and the second contact part, a length of the first contact part in a second direction parallel to the first surface is larger than a length of the second contact part in the second direction.Type: GrantFiled: March 6, 2020Date of Patent: July 27, 2021Assignee: Kioxia CorporationInventors: Tomonari Shioda, Takashi Ishida
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Patent number: 11065832Abstract: A bladder bag is a mold for molding inside of a composite material structure. The composite material structure includes a narrow portion formed by narrowing a part of the inside and a space portion formed so as to be adjacent to the narrow portion. The bladder bag includes a bladder bag main body and a cord-like member. The bladder bag main body includes a narrow molding portion for molding the narrow portion of the composite material structure, a space molding portion for molding the space portion of the composite material structure, and an air intake for introducing air. The cord-like member is provided inside the bladder bag main body, passes through the narrow molding portion from the air intake, and is connected to an inner surface of the space molding portion.Type: GrantFiled: October 13, 2017Date of Patent: July 20, 2021Assignee: MITSUBISHI HEAVY INDUSTRIES, LTD.Inventors: Kiyoka Takagi, Jun Ishida, Sota Kamo, Katsuya Yoshino, Toshio Abe, Koichi Hasegawa, Yoshihiro Sugiyama, Takashi Ishida
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Patent number: 11018217Abstract: A semiconductor device includes a first semiconductor layer that is an electrically-conductive polycrystalline semiconductor layer and a second semiconductor layer on the first semiconductor layer. The second semiconductor layer is an electrically-conductive polycrystalline semiconductor layer having a smaller average grain size than the first semiconductor layer. A plurality of electrode layers are stacked on the second semiconductor layer at intervals in a first direction. A third semiconductor layer extends in the first direction through the first semiconductor layer, the second semiconductor layer, and each of the electrode layers and contacts the second semiconductor layer. A charge storage layer is between the plurality of electrode layers and the third semiconductor layer.Type: GrantFiled: August 23, 2019Date of Patent: May 25, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Takashi Ishida, Takahiro Sugimoto, Hiroshi Kanno, Tatsuya Okamoto
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Publication number: 20210141983Abstract: [Object] To appropriately make apparent the feature part of the object shape. [Solving Means] This technology moves each face in a normal direction of each face from data representing an object shape of a CAD model by discretizing a surface of the CAD model into a grid and arranging faces surrounded by discrete points, to thereby generate an expansion model or a contraction model of the object shape of the CAD model, considers that the surface of the expansion model or the contraction model is uniformly charged and solves a Laplace's equation for an electrostatic field on the surface according to a boundary element method to thereby determine a potential distribution on the surface of the expansion model or the contraction model, and detects a feature part of the object shape on the basis of the determined potential distribution.Type: ApplicationFiled: April 1, 2019Publication date: May 13, 2021Inventors: Masashi KANAMORI, Takashi ISHIDA, Atsushi HASHIMOTO, Takashi AOYAMA
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Publication number: 20210111189Abstract: According to an embodiment, a non-volatile memory device includes first electrodes stacked on an underlying layer, a second electrode provided on the first electrodes, a semiconductor layer extending in a first direction from the underlying layer to the second electrode, and a memory film provided between each of the first electrodes and the semiconductor layer. The semiconductor layer includes a first portion adjacent to the first electrodes and a second portion adjacent to the second electrode. The second portion has a thickness thinner than a thickness of the first portion in a second direction perpendicular to the first direction.Type: ApplicationFiled: December 21, 2020Publication date: April 15, 2021Applicant: Toshiba Memory CorporationInventors: Takashi ISHIDA, Yoshiaki FUKUZUMI, Takayuki OKADA, Masaki TSUJI
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Publication number: 20210074592Abstract: A semiconductor device according to an embodiment includes: a semiconductor substrate including a first surface, a first contact part provided at a deeper level than the first surface, and a second contact part protruding up to a higher level than the first surface from the first contact part; a stacked body in which insulating layers and electrode layers are alternately stacked on the first surface; and a semiconductor film extending, on the second contact part, in the stacked body in a first direction perpendicular to the first surface. At an interface between the first contact part and the second contact part, a length of the first contact part in a second direction parallel to the first surface is larger than a length of the second contact part in the second direction.Type: ApplicationFiled: March 6, 2020Publication date: March 11, 2021Applicant: Kioxia CorporationInventors: Tomonari SHIODA, Takashi ISHIDA
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Publication number: 20210039339Abstract: A method for molding a composite material includes a conductive wire-shaped material arrangement step and a magnetic field application step. The conductive wire-shaped material arrangement step is a step for arranging, in a pre-reaction composite material including reinforcing fibers, a plurality of conductive wire-shaped materials along a direction intersecting the reinforcing fibers with intervals wider than intervals of the reinforcing fibers in a plane on which the reinforcing fibers are arranged. The magnetic field application step is a step for applying a magnetic field in a direction intersecting the plane on which the reinforcing fibers are arranged.Type: ApplicationFiled: January 31, 2019Publication date: February 11, 2021Inventors: Nobuyuki KAMIHARA, Kiyoka TAKAGI, Toshio ABE, Mikio MURAOKA, Toshiyuki TAKAYANAGI, Naomoto ISHIKAWA, Wataru NISHIMURA, Sota KAMO, Tomoharu DENGO, Takashi ISHIDA, Yukihiro YOSHIDA
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Patent number: 10916562Abstract: According to an embodiment, a non-volatile memory device includes first electrodes stacked on an underlying layer, a second electrode provided on the first electrodes, a semiconductor layer extending in a first direction from the underlying layer to the second electrode, and a memory film provided between each of the first electrodes and the semiconductor layer. The semiconductor layer includes a first portion adjacent to the first electrodes and a second portion adjacent to the second electrode. The second portion has a thickness thinner than a thickness of the first portion in a second direction perpendicular to the first direction.Type: GrantFiled: May 14, 2019Date of Patent: February 9, 2021Assignee: Toshiba Memory CorporationInventors: Takashi Ishida, Yoshiaki Fukuzumi, Takayuki Okada, Masaki Tsuji
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Publication number: 20200279864Abstract: A semiconductor memory device includes a substrate, gate electrodes arranged in a thickness direction of the substrate, first and second semiconductor layers, a gate insulating film, and a first contact. The first semiconductor layer extends in the thickness direction and faces the gate electrodes. The gate insulating film is between the gate electrodes and the first semiconductor layer. The second semiconductor layer is between the substrate and the gate electrodes and connected to a side surface of the first semiconductor layer in a surface direction. The first contact extends in the thickness direction and electrically connected to the second semiconductor layer. The second semiconductor layer includes a first region in contact with the side surface of the first semiconductor layer and containing P-type impurities, and a first contact region electrically connected to the first contact and having a higher concentration of N-type impurities than the first region.Type: ApplicationFiled: September 3, 2019Publication date: September 3, 2020Inventors: Ken KOMIYA, Takashi ISHIDA, Hiroshi KANNO
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Patent number: 10751046Abstract: A medical suture needle made of stainless steel includes a cutting blade component and a body part continuing to the cutting blade component. The cutting blade component, whose degree of thickness decreases from the body part to a sharp point, includes a first cutting blade part and a second cutting blade part continuing from the first cutting blade part. The first cutting blade part includes two first slanted surfaces formed sandwiching an apex and a first bottom surface sandwiched by the two first slanted surfaces. Cutting blades are formed at an edge constituting the apex and at edges where the first bottom surface and the two first slanted surfaces intersect. The second cutting blade part includes first slanted surfaces, second slanted surfaces having rims approximately parallel to the apex and formed on the respective first slanted surfaces, and a second bottom surface sandwiched by the second slanted surfaces.Type: GrantFiled: January 6, 2017Date of Patent: August 25, 2020Assignee: MANI, INC.Inventors: Takashi Ishida, Shinichi Akutsu, Motoichi Sugino
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Publication number: 20200189214Abstract: A bladder bag is a mold for molding inside of a composite material structure. The composite material structure includes a narrow portion formed by narrowing a part of the inside and a space portion formed so as to be adjacent to the narrow portion. The bladder bag includes a bladder bag main body and a cord-like member. The bladder bag main body includes a narrow molding portion for molding the narrow portion of the composite material structure, a space molding portion for molding the space portion of the composite material structure, and an air intake for introducing air. The cord-like member is provided inside the bladder bag main body, passes through the narrow molding portion from the air intake, and is connected to an inner surface of the space molding portion.Type: ApplicationFiled: October 13, 2017Publication date: June 18, 2020Inventors: Kiyoka TAKAGI, Jun ISHIDA, Sota KAMO, Katsuya YOSHINO, Toshio ABE, Koichi HASEGAWA, Yoshihiro SUGIYAMA, Takashi ISHIDA
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Patent number: 10658295Abstract: According to one embodiment, a semiconductor memory device includes a first interconnect layer, a first insulating layer, a second interconnect layer, and a memory pillar including a second insulating layer, a charge storage layer, and a third insulating layer stacked on a part of a side surface and on the bottom surface of the memory pillar, and a first silicide layer in contact with the first interconnect layer, a semiconductor layer, and a second silicide layer stacked in order along a first direction. A height position of a bottom surface of the first silicide layer is lower than a top surface of the first interconnect layer, and a height position of a top surface of the first silicide layer is higher than a bottom surface of the second interconnect layer.Type: GrantFiled: September 10, 2018Date of Patent: May 19, 2020Assignee: Toshiba Memory CorporationInventors: Tomoya Kawai, Takashi Ishida, Shuichi Toriyama
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Publication number: 20200127081Abstract: A semiconductor device includes a first semiconductor layer that is an electrically-conductive polycrystalline semiconductor layer and a second semiconductor layer on the first semiconductor layer. The second semiconductor layer is an electrically-conductive polycrystalline semiconductor layer having a smaller average grain size than the first semiconductor layer. A plurality of electrode layers are stacked on the second semiconductor layer at intervals in a first direction. A third semiconductor layer extends in the first direction through the first semiconductor layer, the second semiconductor layer, and each of the electrode layers and contacts the second semiconductor layer. A charge storage layer is between the plurality of electrode layers and the third semiconductor layer.Type: ApplicationFiled: August 23, 2019Publication date: April 23, 2020Inventors: Takashi ISHIDA, Takahiro SUGIMOTO, Hiroshi KANNO, Tatsuya OKAMOTO