Patents by Inventor Takashi Ishida

Takashi Ishida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10591863
    Abstract: An image forming apparatus includes an apparatus body, a wall face of the apparatus body having an ejection opening from which a sheet conveyed in a first direction is ejected, a sheet support to support the sheet discharged from the discharge opening in the first direction, and a mount to mount the sheet support to the apparatus body. The mount includes an abutting portion including an abutting face that contacts a wall face of the apparatus body, and a projection projecting in a second direction opposite to the first direction from the abutting face. The abutting face extends in a vertically downward direction from the projection, and the projection is fixed to the apparatus body in a vertical direction.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: March 17, 2020
    Assignee: Ricoh Company, Ltd.
    Inventors: Takashi Ishida, Goro Katsuyama
  • Patent number: 10575845
    Abstract: Strength of a front end part having a sharp point of a medical suture needle is maintained and resistance when piercing tissue is reduced. There is provided a medical suture needle having a triangular cross section made of austenitic stainless steel having a fibrously extending structure, having two first slanted surfaces (11) ground and sandwiching a ridge (20), and a bottom surface (13) sandwiched between the two first slanted surfaces and ground. The ridge is formed comprising a first cutting blade (1) that is formed by the two first slanted surfaces (11) intersecting, a ridge part (20) that is formed on a body part side of the first cutting blade without the first slanted surfaces (11) intersecting, and a second cutting blade (2) that is formed by two second slanted surfaces (12) ground, intersecting and sandwiching the first cutting blade (1) on a front end side of the first cutting blade (1).
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: March 3, 2020
    Assignee: MANI, INC.
    Inventors: Masaaki Matsutani, Shinichi Akutsu, Masato Mizui, Takashi Ishida
  • Patent number: 10562243
    Abstract: A core (20) and a bag (22, 24) are provided which are used to shape an FRP structure (10; 30). The bag (22, 24) has a core bag section (24) which covers the outer circumference of the core (20), and a coverture bag section (22) which covers a plurality of fiber components (12, 14; 12, 14, 16).
    Type: Grant
    Filed: January 27, 2015
    Date of Patent: February 18, 2020
    Assignee: MITSUBISHI HEAVY INDUSTRIES, LTD.
    Inventors: Toshio Abe, Kiyoka Takagi, Takayuki Koyama, Katsuya Yoshino, Kazuaki Kishimoto, Koichi Saito, Takashi Ishida
  • Publication number: 20190355742
    Abstract: A semiconductor memory device includes a plurality of electrode layers stacked above a first semiconductor layer, a second semiconductor layer and a first film. The second semiconductor layer extends through the plurality of electrode layers in a stacking direction of the plurality of electrode layers. The second semiconductor layer includes an end portion inside the first semiconductor layer. The first film is positioned inside the first semiconductor layer and contacts the first semiconductor layer. The first semiconductor layer includes a first portion, a second portion, and a third portion. The first film is positioned between the first portion and the second portion. The third portion links the first portion and the second portion. The third portion is positioned between the first film and the second semiconductor layer. The second semiconductor layer includes a contact portion contacting the third portion of the first semiconductor layer.
    Type: Application
    Filed: March 8, 2019
    Publication date: November 21, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Takayuki MARUYAMA, Yoshiaki Fukuzumi, Yuki Sugiura, Shinya Arai, Fumie Kikushima, Keisuke Suda, Takashi Ishida
  • Publication number: 20190295956
    Abstract: According to one embodiment, a semiconductor memory device includes a first interconnect layer, a first insulating layer, a second interconnect layer, and a memory pillar including a second insulating layer, a charge storage layer, and a third insulating layer stacked on a part of a side surface and on the bottom surface of the memory pillar, and a first silicide layer in contact with the first interconnect layer, a semiconductor layer, and a second silicide layer stacked in order along a first direction. A height position of a bottom surface of the first silicide layer is lower than a top surface of the first interconnect layer, and a height position of a top surface of the first silicide layer is higher than a bottom surface of the second interconnect layer.
    Type: Application
    Filed: September 10, 2018
    Publication date: September 26, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Tomoya Kawai, Takashi Ishida, Shuichi Toriyama
  • Publication number: 20190267398
    Abstract: According to an embodiment, a non-volatile memory device includes first electrodes stacked on an underlying layer, a second electrode provided on the first electrodes, a semiconductor layer extending in a first direction from the underlying layer to the second electrode, and a memory film provided between each of the first electrodes and the semiconductor layer. The semiconductor layer includes a first portion adjacent to the first electrodes and a second portion adjacent to the second electrode. The second portion has a thickness thinner than a thickness of the first portion in a second direction perpendicular to the first direction.
    Type: Application
    Filed: May 14, 2019
    Publication date: August 29, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Takashi ISHIDA, Yoshiaki FUKUZUMI, Takayuki OKADA, Masaki TSUJI
  • Patent number: 10340285
    Abstract: According to an embodiment, a non-volatile memory device includes first electrodes stacked on an underlying layer, a second electrode provided on the first electrodes, a semiconductor layer extending in a first direction from the underlying layer to the second electrode, and a memory film provided between each of the first electrodes and the semiconductor layer. The semiconductor layer includes a first portion adjacent to the first electrodes and a second portion adjacent to the second electrode. The second portion has a thickness thinner than a thickness of the first portion in a second direction perpendicular to the first direction.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: July 2, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takashi Ishida, Yoshiaki Fukuzumi, Takayuki Okada, Masaki Tsuji
  • Patent number: 10290078
    Abstract: An image processing apparatus includes circuitry that converts user voices that are input into a string of characters reflecting a statement made with the user voices, retrieves one or more items of information related to the string, stores the information being retrieved associated with identification information indicating a retrieval time when the information is retrieved, draws a graphical image including the information being stored on a projection target image to be projected by a projector, and controls the projector to project the projection target image including the graphical image, the graphical image having a size that is determined in accordance with the identification information associated with the information included in the graphical image being projected.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: May 14, 2019
    Assignee: Ricoh Company, Ltd.
    Inventors: Ryotaro Fujiyama, Takashi Ishida, Naoto Tsuruoka, Kyoko Hashimoto, Shin Yamauchi
  • Patent number: 10283647
    Abstract: According to one embodiment, a semiconductor device includes an interconnection layer, a stacked body, a plurality of separation portions, a semiconductor body, a charge storage portion, an n-type semiconductor region, and a p-type semiconductor region. The n-type semiconductor region is provided between the separation portion and the first interconnection part, and has contact with the first interconnection part and the second semiconductor part. The p-type semiconductor region is provided between the separation portion and the second interconnection part, and has contact with the second interconnection part and the second semiconductor part.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: May 7, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Koji Matsuo, Gaku Sudo, Jun Nogami, Tatsuro Shinozaki, Takashi Ishida, Jun Fujiki, Kenzo Manabe
  • Patent number: 10195789
    Abstract: This structure is provided with a first composite material 11, a second composite material 12 joined to the first composite material 11 by a film adhesive 21 provided between the first composite material 11 and the second composite material 12, and a corner fillet part 13 provided on a corner part 15 formed by the first composite material 11 and the second composite material 12. The shape of the corner fillet part 13 is a design shape P designed in advance, and the corner fillet part 13 is formed by curing the film adhesive 21 after arranging the film adhesive 21 on the corner part 15 so as to fit into the design shape P.
    Type: Grant
    Filed: October 7, 2015
    Date of Patent: February 5, 2019
    Assignee: MITSUBISHI HEAVY INDUSTRIES, LTD.
    Inventors: Toshio Abe, Kiyoka Takagi, Takayuki Koyama, Kazuaki Kishimoto, Koichi Saito, Takashi Ishida
  • Publication number: 20190008513
    Abstract: A medical suture needle made of stainless steel includes a cutting blade component and a body part continuing to the cutting blade component. The cutting blade component, whose degree of thickness decreases from the body part to a sharp point, includes a first cutting blade part and a second cutting blade part continuing from the first cutting blade part. The first cutting blade part includes two first slanted surfaces formed sandwiching an apex and a first bottom surface sandwiched by the two first slanted surfaces. Cutting blades are formed at an edge constituting the apex and at edges where the first bottom surface and the two first slanted surfaces intersect. The second cutting blade part includes first slanted surfaces, second slanted surfaces having rims approximately parallel to the apex and formed on the respective first slanted surfaces, and a second bottom surface sandwiched by the second slanted surfaces.
    Type: Application
    Filed: January 6, 2017
    Publication date: January 10, 2019
    Applicant: MANI, Inc.
    Inventors: Takashi Ishida, Shinichi Akutsu, Motoichi Sugino
  • Patent number: 10071794
    Abstract: Provided is a joint and an aircraft structure wherein it is possible to position a member relative to a preform with high accuracy. A groove into which a plate member (30) is inserted is formed in a pi-shaped joint (20) provided on the preform (21), and the preform (21) and the plate member (30) are connected by being bonded. Moreover, a fitting shape (32A-1) into which the plate member (30) is fitted is formed on the pi-shaped joint (20) on the whole groove bottom face. Additionally, a fitting shape (32A-2) into which the plate member (30) is fitted is formed on a portion of the groove bottom face. Furthermore, fitting shapes (32B-1, 32B-2), into which the groove bottom face that is formed on the pi-shaped joint (20) is fitted, are formed on the surface of the plate material (30) that is fitted with the pi-shaped joint (20).
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: September 11, 2018
    Assignee: MITSUBISHI HEAVY INDUSTRIES, LTD.
    Inventors: Toshio Abe, Kiyoka Takagi, Takayuki Koyama, Kazuaki Kishimoto, Kouichi Saito, Takashi Ishida
  • Patent number: 10040538
    Abstract: A joint (20) joins a plate member (26) with a preform (22), wherein an inclined part (28), which is inclined relative to a surface that is orthogonal to the direction in which a tensile load is applied to the plate member (26), is formed on a surface (25) that joins with the preform (22). Moreover, an indented part (38) corresponding to the shape of the inclined part (28) is formed on the preform (22) so that the inclined part (28) of the joint (20) is embedded into the indented part (38). The joint (20) is embedded in and bonded to the preform (22).
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: August 7, 2018
    Assignee: Mitsubishi Heavy Industries, Ltd.
    Inventors: Toshio Abe, Kiyoka Takagi, Takayuki Koyama, Kazuaki Kishimoto, Kouichi Saito, Takashi Ishida
  • Publication number: 20180211971
    Abstract: According to an embodiment, a non-volatile memory device includes first electrodes stacked on an underlying layer, a second electrode provided on the first electrodes, a semiconductor layer extending in a first direction from the underlying layer to the second electrode, and a memory film provided between each of the first electrodes and the semiconductor layer. The semiconductor layer includes a first portion adjacent to the first electrodes and a second portion adjacent to the second electrode. The second portion has a thickness thinner than a thickness of the first portion in a second direction perpendicular to the first direction.
    Type: Application
    Filed: March 22, 2018
    Publication date: July 26, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Takashi ISHIDA, Yoshiaki Fukuzumi, Takayuki Okada, Masaki Tsuji
  • Patent number: 9997535
    Abstract: According to an embodiment, a semiconductor memory device comprises: control gate electrodes stacked above a substrate; a semiconductor layer that extends in a first direction above the substrate and faces the control gate electrodes; and a gate insulating layer provided between these control gate electrode and semiconductor layer. The gate insulating layer comprises: a first insulating layer covering a side surface of the semiconductor layer; a charge accumulation layer covering a side surface of this first insulating layer; and a second insulating layer including a metal oxide and covering a side surface of this charge accumulation layer. The charge accumulation layer has: a first portion facing the control gate electrode; and a second portion facing a region between control gate electrodes adjacent in the first direction and including more oxygen than the first portion.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: June 12, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Takashi Ishida
  • Patent number: 9991278
    Abstract: According to an embodiment, a non-volatile memory device includes first electrodes stacked on an underlying layer, a second electrode provided on the first electrodes, a semiconductor layer extending in a first direction from the underlying layer to the second electrode, and a memory film provided between each of the first electrodes and the semiconductor layer. The semiconductor layer includes a first portion adjacent to the first electrodes and a second portion adjacent to the second electrode. The second portion has a thickness thinner than a thickness of the first portion in a second direction perpendicular to the first direction.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: June 5, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takashi Ishida, Yoshiaki Fukuzumi, Takayuki Okada, Masaki Tsuji
  • Patent number: 9948223
    Abstract: Provided is drive unit of a synchronous motor capable of improving the accuracy of magnetic flux operations with a simple configuration. To this end, the drive unit has a magnetic flux operation part which, in the case where a direction of a magnetic field pole of the synchronous motor is regarded as a d-axis and a direction orthogonal to the d-axis is regarded as a q-axis, calculates a magnetic flux of the d-axis and a magnetic flux of the q-axis on the basis of a current of the d-axis, a current of the q-axis, and a field current of the synchronous motor; and a magnetic flux operation error correcting part which calculates a phase difference between an input voltage and an input current of the synchronous motor and corrects an inner-phase difference angle calculated from the magnetic flux of the d-axis and the magnetic flux of the q-axis on the basis of the phase difference.
    Type: Grant
    Filed: September 3, 2012
    Date of Patent: April 17, 2018
    Assignee: TOSHIBA MITSUBISHI-ELECTRIC INDUSTRIAL SYSTEMS CORPORATION
    Inventor: Takashi Ishida
  • Patent number: 9934860
    Abstract: A semiconductor memory device includes first to fourth electrodes; first and second semiconductor members; a first charge storage member provided between the first semiconductor member and the first electrode; a first interconnect connected to the second electrode side of the first semiconductor member and to the fourth electrode side of the second semiconductor member; and a control circuit. The control circuit sets the first interconnect to a floating state, causes a potential of the third electrode side of the second semiconductor member to increase to a first potential, causes the potential of the third electrode to increase to a second potential lower than the first potential, causes the potential of the second electrode to increase to a third potential lower than the first potential, applies a fourth potential lower than the second and the third potentials to the first electrode, and sets the fourth electrode to a floating state.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: April 3, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Takashi Ishida
  • Publication number: 20180090210
    Abstract: A semiconductor memory device includes first to fourth electrodes; first and second semiconductor members; a first charge storage member provided between the first semiconductor member and the first electrode; a first interconnect connected to the second electrode side of the first semiconductor member and to the fourth electrode side of the second semiconductor member; and a control circuit. The control circuit sets the first interconnect to a floating state, causes a potential of the third electrode side of the second semiconductor member to increase to a first potential, causes the potential of the third electrode to increase to a second potential lower than the first potential, causes the potential of the second electrode to increase to a third potential lower than the first potential, applies a fourth potential lower than the second and the third potentials to the first electrode, and sets the fourth electrode to a floating state.
    Type: Application
    Filed: March 8, 2017
    Publication date: March 29, 2018
    Applicant: Toshiba Memory Corporation
    Inventor: Takashi ISHIDA
  • Patent number: D826322
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: August 21, 2018
    Assignee: RICOH COMPANY, LTD.
    Inventors: Takashi Ishida, Goro Katsuyama