Abstract: In an embodiment, a sensor module 10 includes a piezoelectric element 30 placed on the principal face of a board 20, which piezoelectric element is surrounded by a vibration ring 40 and installed in an appropriate position on a person's arm, neck, etc., using a medical fixing tape, etc., with the vibration ring 40 contacting the person's skin. When a pulse wave is transmitted to the vibration ring 40 from the skin, the board 20 also vibrates and this vibration is transmitted to the piezoelectric element 30. Then, the piezoelectric element 30 is displaced and the pulse wave vibration is converted to an electrical signal. The resulting electrical signal is amplified by an amplifier on the board 20 and input to the vibration analysis device 100, where prescribed calculations are run to perform waveform analysis. The vascular state, etc., can be known from pulse waveforms.

Abstract: According to one embodiment, a storage device includes a processor which executes first processing, second processing and third processing. The second processing includes processing for relaying a command issued by a host device, and an execution result of the first processing corresponding to the. command, between the host device and the first processing. The third processing includes processing for causing the second processing to transition from a first state to a second state of lower energy consumption than the first state, when a first period in which the second processing is in an idle state exceeds a second period. The third processing further includes processing for maintaining the first state under a first condition, when the first period exceeds the second period.

Abstract: [Problem] To provide a motor protein device capable of efficiently transporting and detecting a target antibody. [Solution] A motor protein device of the present invention includes a collection region where a carrier molecule collects a target molecule using antigen-antibody reaction, and an unloading region where the target molecule is unloaded from the carrier molecule using chemical equilibrium. Further, the motor protein device includes a transport path provided between the collection region and the unloading region through which the carrier molecule can transport the target molecule, and an analysis portion which detects a change in concentration of the target molecule in the unloading region. The unloading region includes certain antibody having capture force higher than predetermined antibody being modified to the carrier molecule and the target molecule is concentrated in the unloading region.

Abstract: According to one embodiment, a storage device includes a processor which executes first processing, second processing and third processing. The second processing includes processing for relaying a command issued by a host device, and an execution result of the first processing corresponding to the. command, between the host device and the first processing. The third processing includes processing for causing the second processing to transition from a first state to a second state of lower energy consumption than the first state, when a first period in which the second processing is in an idle state exceeds a second period. The third processing further includes processing for maintaining the first state under a first condition, when the first period exceeds the second period.

Abstract: Disclosed is a semiconductor device which is intended to reduce the total number of storage element blocks that constitute a desired logic circuit. The semiconductor device includes N address lines (N is an integer equal to two or more), N data lines, and a plurality of storage sections. Each of the storage sections includes an address decoder for decoding an address supplied via the N address lines to output a word select signal to word lines; and a plurality of storage elements which are connected to the word lines and the data lines, each store data that constitute a truth table, and input or output the data via the data lines in accordance with the word select signal supplied via the word lines. The semiconductor device is adapted such that the N address lines for the storage sections are connected to the respective data lines of other N ones of the storage sections, while the N data lines for the storage sections are connected to the respective address lines of other N ones of the storage sections.

Abstract: According to one embodiment, in a memory system, the overlap checker is configured to perform a preliminary check operation that checks whether or not there is a logical address overlap between a first command and a second command. The first command is received by the host interface. The second command is received prior to the first command. The second command is an uncompleted command. The overlap checker is configured to queue a command received by the host interface in the command queue, and perform a recheck operation that checks whether or not there is a logical address overlap between a third command and a fourth command. The fourth command is received prior the third command. The fourth command is an uncompleted command. The third command includes an overlapped logical address detected by the preliminary check operation. The third command is dequeued by the command execution processing unit.

Abstract: A buffer controller has a buffer for holding plural sets of data contained in a packet entered from a telecommunications network, a codec converter and a controller. When receiving a packet, the buffer controller has the controller put data, in the packet, in a storage position in the buffer corresponding to the sequence number of the packet, and makes a decision as to whether or not the codec conversion is to be performed. If packets are out of sequence, lost or dropped during communication, the buffer controller can correct the packet order and compensate the packet loss with the minimum delay.

Abstract: According to one embodiment, a data transfer control device complying with a communication protocol which executes an update of information from an attachment device in a predetermined area of a system memory, the device includes a receiving part receiving the information from the attachment device, a transferring part transferring the information in the predetermined area, the information from the transferring part overwritten in the predetermined area sequentially, and a determining part inhibiting a transfer of the information in the transferring part to omit the update of the information in the predetermined area.

Abstract: Disclosed is a semiconductor device which is intended to reduce the total number of storage element blocks that constitute a desired logic circuit. The semiconductor device includes N address lines (N is an integer equal to two or more), N data lines, and a plurality of storage sections. Each of the storage sections includes an address decoder for decoding an address supplied via the N address lines to output a word select signal to word lines; and a plurality of storage elements which are connected to the word lines and the data lines, each store data that constitute a truth table, and input or output the data via the data lines in accordance with the word select signal supplied via the word lines. The semiconductor device is adapted such that the N address lines for the storage sections are connected to the respective data lines of other N ones of the storage sections, while the N data lines for the storage sections are connected to the respective address lines of other N ones of the storage sections.

Abstract: According to one embodiment, a data transfer control device complying with a communication protocol which executes an update of information from an attachment device in a predetermined area of a system memory, the device includes a receiving part receiving the information from the attachment device, a transferring part transferring the information in the predetermined area, the information from the transferring part overwritten in the predetermined area sequentially, and a determining part inhibiting a transfer of the information in the transferring part to omit the update of the information in the predetermined area.

Abstract: A semiconductor device of this invention has an array of non-volatile memory cells, may operate immediately after power activation to write data on and read out the data without reading from an external portion. Further, this invention is free from the lithographic process of the phase-change layer on the manufacturing process.

Abstract: Disclosed is a semiconductor device which is intended to reduce the total number of storage element blocks that constitute a desired logic circuit. The semiconductor device includes N address lines (N is an integer equal to two or more), N data lines, and a plurality of storage sections. Each of the storage sections includes an address decoder for decoding an address supplied via the N address lines to output a word select signal to word lines; and a plurality of storage elements which are connected to the word lines and the data lines, each store data that constitute a truth table, and input or output the data via the data lines in accordance with the word select signal supplied via the word lines. The semiconductor device is adapted such that the N address lines for the storage sections are connected to the respective data lines of other N ones of the storage sections, while the N data lines for the storage sections are connected to the respective address lines of other N ones of the storage sections.

Abstract: [Problem] To provide a motor protein device capable of efficiently transporting and detecting a target antibody. [Solution] A motor protein device of the present invention includes a collection region where a carrier molecule collects a target molecule using antigen-antibody reaction, and an unloading region where the target molecule is unloaded from the carrier molecule using chemical equilibrium. Further, the motor protein device includes a transport path provided between the collection region and the unloading region through which the carrier molecule can transport the target molecule, and an analysis portion which detects a change in concentration of the target molecule in the unloading region. The unloading region includes certain antibody having capture force higher than predetermined antibody being modified to the carrier molecule and the target molecule is concentrated in the unloading region.

Abstract: A magnetic resonance imaging apparatus includes a bore configured to accommodate a subject therein, an RF coil positioned about the bore, and an RF shield positioned about the RF coil. The RF coil includes a first portion positioned adjacent a lower surface side of the bore and spaced a distance from the RF shield that is larger than a distance between a second portion of the RF coil and an upper surface side of the bore.

Abstract: A semiconductor device of this invention has an array of non-volatile memory cells, may operate immediately after power activation to write data on and read out the data without reading from an external portion. Further, this invention is free from the lithographic process of the phase-change layer on the manufacturing process.

Abstract: Disclosed is a semiconductor device which is intended to reduce the total number of storage element blocks that constitute a desired logic circuit. The semiconductor device includes N address lines (N is an integer equal to two or more), N data lines, and a plurality of storage sections. Each of the storage sections includes an address decoder for decoding an address supplied via the N address lines to output a word select signal to word lines; and a plurality of storage elements which are connected to the word lines and the data lines, each store data that constitute a truth table, and input or output the data via the data lines in accordance with the word select signal supplied via the word lines. The semiconductor device is adapted such that the N address lines for the storage sections are connected to the respective data lines of other N ones of the storage sections, while the N data lines for the storage sections are connected to the respective address lines of other N ones of the storage sections.

Abstract: A buffer controller has a buffer for holding plural sets of data contained in a packet entered from a telecommunications network, a codec converter and a controller. When receiving a packet, the buffer controller has the controller put data, in the packet, in a storage position in the buffer corresponding to the sequence number of the packet, and makes a decision as to whether or not the codec conversion is to be performed. If packets are out of sequence, lost or dropped during communication, the buffer controller can correct the packet order and compensate the packet loss with the minimum delay.

Abstract: A jitter buffer control apparatus has a buffer for storing data included in an input packet transmitted from a telecommunications network, and a jitter buffer controller for controlling the buffer to store the input data into the buffer and take out the stored data from the buffer on the basis of a sequence number included in the input packet in a processing period. When under-running occurs in the buffer, the jitter buffer controller stores input data into the buffer with a storage location skipped which corresponds to the processing period associated with packet loss due to the under-running.

Abstract: FPGAs and MPLDs, which are conventional programmable semiconductor devices, have had poor cost performance and did not suitably take long signal lines into account. To solve this, a flip-flop is built into each MLUT block comprised of a plurality of MLUTs, each MLUT comprising a memory and an address-data pair. With respect to the adjacent line between adjacent MLUTs, alternated adjacent line are introduced, while in the case of interconnects between non-adjacent MLUTs, dedicated distant line and, furthermore, a torus interconnect network are provided.

Abstract: A magnetic resonance imaging apparatus includes a bore configured to accommodate a subject therein, an RF coil positioned about the bore, and an RF shield positioned about the RF coil. The RF coil includes a first portion positioned adjacent a lower surface side of the bore and spaced a distance from the RF shield that is larger than a distance between a second portion of the RF coil and an upper surface side of the bore.