Patents by Inventor Takashi Kariya
Takashi Kariya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8124882Abstract: A multilayer printed wiring board 10 includes: a mounting portion 60 on the top surface of which is mounted a semiconductor element that is electrically connected to a wiring pattern 32, etc.; and a capacitor portion 40 having a high dielectric constant layer 43, formed of ceramic and first and second layer electrodes 41 and 42 that sandwich the high dielectric constant layer 43. One of either of the first and second layer electrodes 41 and 42 is connected to a power supply line of the semiconductor element and the other of either of the first and second layer electrodes 41 and 42 is connected to a ground line. In this multilayer printed wiring board 10, high dielectric constant layer 43 included in the layered capacitor portion 40, which is connected between the power supply line and the ground line, is formed of ceramic.Type: GrantFiled: April 6, 2009Date of Patent: February 28, 2012Assignee: Ibiden Co., Ltd.Inventors: Takashi Kariya, Akira Mochida
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Publication number: 20120032335Abstract: An electronic component including a wiring board having a power-source pattern and a signal pattern, a semiconductor element mounted on the wiring board and having a power-source electrode pad and a signal electrode pad, a first connection portion being made of a conductive material and connecting the signal pattern of the wiring board and the signal electrode pad of the semiconductor element, and a second connection portion being made of a conductive material and connecting the power-source pattern of the wiring board and the power-source electrode pad of the semiconductor element. The conductive material of the first connection portion and the conductive material of the second connection portion are selected such that the conductive material of the second connection portion has an electrical resistance which is lower than an electrical resistance of the conductive material of the first connection portion.Type: ApplicationFiled: August 8, 2011Publication date: February 9, 2012Applicant: IBIDEN CO., LTD.Inventors: Takashi KARIYA, Toshiki Furutani, Shinobu Kato
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Patent number: 8108990Abstract: A printed circuit board including a conductor portion, an insulating layer formed over the conductor portion, a thin-film capacitor formed over the insulating layer and including a first electrode, a second electrode and a high-dielectric layer interposed between the first electrode and the second electrode, and a via-hole conductor structure formed through the second electrode and insulating layer and electrically connecting the second electrode and the conductor portion. The via-hole conductor structure has a first portion in the second electrode and a second portion in the insulating layer. The first portion of the via-hole conductor structure has a truncated-cone shape tapering toward the conductor portion.Type: GrantFiled: October 22, 2008Date of Patent: February 7, 2012Assignee: Ibiden Co., Ltd.Inventors: Takashi Kariya, Hironori Tanaka
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Patent number: 8091223Abstract: A method for manufacturing a board with a built-in electronic element, includes providing a support substrate including a support base and a metal foil, forming a protective film made of a metal material on the metal foil of the support substrate, forming a conductive pattern made of a metal material on the protective film by an additive method, placing an electronic element on the support substrate with the conductive pattern such that a surface of the electronic element where a circuit is formed faces the conductive pattern, covering the electronic element with an insulative resin, etching away the metal foil using a first etching solution such that the protective film is not dissolved by the first etching solution or that the protective film has an etching speed which is slower than an etching speed of the metal foil, and electrically connecting terminals of the electronic element and a part of the conductive pattern.Type: GrantFiled: June 27, 2008Date of Patent: January 10, 2012Assignee: IBIDEN Co., Ltd.Inventors: Takashi Kariya, Toshiki Furutani
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Patent number: 8093508Abstract: A printed wiring board including a first insulating layer, a second insulating layer formed over the first insulating layer, a capacitor portion including an upper electrode, a lower electrode and a ceramic high dielectric layer formed between the upper electrode and the lower electrode, the capacitor portion sandwiched by the first insulating layer and the second insulating layer, an upper electrode connecting portion passing through the capacitor portion without contact and through the second insulating layer and electrically connected to the upper electrode of the capacitor portion, and a lower electrode connecting portion passing through the second insulating layer and the upper electrode of the capacitor portion without contact and electrically connected to the lower electrode in contact.Type: GrantFiled: April 13, 2010Date of Patent: January 10, 2012Assignee: Ibiden Co., Ltd.Inventors: Takashi Kariya, Akira Mochida
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Publication number: 20120000068Abstract: A method for manufacturing a printed circuit board, including providing a core substrate having an electronic component accommodated in the core substrate; forming a positioning mark on the core substrate; forming an interlayer insulating layer over the core substrate, the positioning mark and the electronic component; forming a via hole opening connecting to the electronic component through the interlayer insulating layer in accordance with the positioning mark on the core substrate; and forming a via hole structure in the via hole opening in the interlayer insulating layer such that the via hole structure is electrically connected to the electronic component.Type: ApplicationFiled: September 16, 2011Publication date: January 5, 2012Applicant: IBIDEN CO., LTD.Inventors: Hajime SAKAMOTO, Tadashi Sugiyama, Dongdong Wang, Takashi Kariya
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Patent number: 8079142Abstract: A method for manufacturing a printed circuit board, including providing a core substrate and an electronic component contained in the core substrate, the electronic component having a die pad, forming a positioning mark on the core substrate, forming an interlayer insulating layer over the core substrate and the electronic component, forming a via hole opening connecting to the die pad of the electronic component through the interlayer insulating layer in accordance with the positioning mark on the core substrate, and forming a via hole structure in the via hole opening in the interlayer insulating layer such that the via hole structure is electrically connected to the die pad.Type: GrantFiled: November 19, 2008Date of Patent: December 20, 2011Assignee: Ibiden Co., Ltd.Inventors: Hajime Sakamoto, Tadashi Sugiyama, Dongdong Wang, Takashi Kariya
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Publication number: 20110290544Abstract: A printed wiring board including a core substrate, a build-up layer formed over the core substrate and including a first insulating layer, a conductor layer formed over the first insulating layer, and a second insulating layer formed over the conductor layer, and one or more wiring patterns formed over the first insulating layer. The conductor layer includes conductor portions, and the conductor portions have notched portions, respectively, facing each other across the wiring pattern.Type: ApplicationFiled: August 9, 2011Publication date: December 1, 2011Applicant: IBIDEN CO., LTD.Inventors: Naohiro Hirose, Takashi Kariya, Yoji Mori
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Patent number: 8046914Abstract: A method of manufacturing a multilayer printed circuit board having interlayer insulating layers and conductor layers repeatedly formed on a substrate, via holes formed in the interlayer insulating layers, and establishing electrical connection through the via holes, including containing an electronic component in said substrate, removing a film on a surface of a die pad of said electronic component, forming a mediate layer to be connected to a via hole of a lowermost interlayer insulating layer, on said die pad, forming the interlayer insulating layers on said substrate, and forming the via holes connected to the conductor circuits and the mediate layers, in said interlayer resin insulating layers.Type: GrantFiled: October 1, 2009Date of Patent: November 1, 2011Assignee: Ibiden Co., Ltd.Inventors: Hajime Sakamoto, Tadashi Sugiyama, Dongdong Wang, Takashi Kariya
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Publication number: 20110259629Abstract: A method of producing a capacitor for a printed circuit board includes producing high-dielectric sheets and selecting ones of the high-dielectric sheets, which are substantially free from a defect after the heat process. Each of the high-dielectric sheets is produced by providing a first electrode, forming a first sputter film on the first electrode, forming an intermediate layer on the first sputter film by calcining a sol-gel film, forming a second sputter film on the intermediate layer, and providing a second electrode on the second sputter film. The high-dielectric sheets are subjected to a heat process in which the high-dielectric sheets are subjected to a first temperature at least once and a second temperature higher than the first temperature at least once.Type: ApplicationFiled: July 1, 2011Publication date: October 27, 2011Applicant: IBIDEN CO., LTD.Inventors: Takashi KARIYA, Hironori Tanaka
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Publication number: 20110240357Abstract: A wiring board including a first substrate having a penetrating hole penetrating through the first substrate, a built-up layer formed on one surface of the first substrate and including multiple interlayer resin insulation layers and wiring layers, the built-up layer having an opening portion communicated with the penetrating hole of the first substrate and opened to the outermost surface of the built-up layer, an interposer accommodated in the opening portion of the built-up layer and including a second substrate and a wiring layer formed on the second substrate, the wiring layer of the interposer including multiple conductive circuits for being connected to multiple semiconductor elements, and a filler filling the opening portion of the built-up layer such that the interposer is held in the opening portion of the built-up layer. The opening portion of the built-up layer has a tapered portion tapering toward the outermost surface of the built-up layer.Type: ApplicationFiled: March 17, 2011Publication date: October 6, 2011Applicant: IBIDEN CO., LTDInventors: Takashi Kariya, Toshiki Furutani
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Patent number: 8018046Abstract: A printed wiring board including a core substrate, a build-up layer formed over the core substrate and including a first insulating layer, a conductor layer formed over the first insulating layer, and a second insulating layer formed over the conductor layer, and one or more wiring patterns formed over the first insulating layer. The conductor layer includes conductor portions, and the conductor portions have notched portions, respectively, facing each other across the wiring pattern.Type: GrantFiled: February 20, 2009Date of Patent: September 13, 2011Assignee: IBIDEN Co., Ltd.Inventors: Naohiro Hirose, Takashi Kariya, Yoji Mori
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Patent number: 8008583Abstract: This invention provides a multilayer printed wiring board which achieves fine pitches. A heat resistant substrate is incorporated in a multilayer printed wiring board and interlayer resin insulation layer and conductive layer are placed alternately on the heat resistant substrate. A built-up wiring board in which respective conductive layers are connected by via hole is formed. A via hole is formed on the surface of a mirror-processed Si substrate by using a heat resistant substrate composed of Si substrate so that finer wiring than a resin substrate having unevenness in its surface can be formed, whereby achieving fine pitches. Further, by forming the wiring on a mirror processed surface, dispersion of wiring decreases thereby decreasing dispersion of impedance.Type: GrantFiled: December 8, 2008Date of Patent: August 30, 2011Assignee: IBIDEN Co., Ltd.Inventors: Takashi Kariya, Toshiki Furutani, Takeshi Kawanishi
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Patent number: 7994432Abstract: A circuit wiring board including a wiring substrate, and a heat resistant substrate accommodated in the wiring substrate and having a thermal expansion coefficient in a range between 3 ppm to 10 ppm and including a core substrate and a built-up wiring layer formed over the core substrate, the built-up wiring layer including conductive layers, interlayer resin insulating layers and a via hole conductor connecting the conductive layers through one of the interlayer resin insulating layers.Type: GrantFiled: June 19, 2009Date of Patent: August 9, 2011Assignee: Ibiden Co., Ltd.Inventors: Takashi Kariya, Toshiki Furutani, Takeshi Kawanishi
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Patent number: 7982139Abstract: A multilayer printed wiring board 10 includes: a mounting portion 60 on the top surface of which is mounted a semiconductor element that is electrically connected to a wiring pattern 32, etc.; and a capacitor portion 40 having a high dielectric constant layer 43, formed of ceramic and first and second layer electrodes 41 and 42 that sandwich the high dielectric constant layer 43. One of either of the first and second layer electrodes 41 and 42 is connected to a power supply line of the semiconductor element and the other of either of the first and second layer electrodes 41 and 42 is connected to a ground line. In this multilayer printed wiring board 10, high dielectric constant layer 43 included in the layered capacitor portion 40, which is connected between the power supply line and the ground line, is formed of ceramic.Type: GrantFiled: February 17, 2006Date of Patent: July 19, 2011Assignee: Ibiden Co. Ltd.Inventors: Takashi Kariya, Akira Mochida
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Patent number: 7971354Abstract: A multilayer printed wiring board manufacturing method including forming conductor posts, which are of substantially uniform thickness and with which the top surfaces are protected by a resist, on a conductor pattern disposed on an upper surface of a build-up layer formed on a core substrate, shaping the conductor posts to have a constriction by adjusting the time of immersion in an etching solution that etches the conductor posts, forming a low elastic modulus layer of substantially the same height as the conductor posts after removing the resist at the top surfaces, and forming mounting electrodes on upper surfaces of the conductor posts.Type: GrantFiled: January 5, 2010Date of Patent: July 5, 2011Assignee: Ibiden Co., Ltd.Inventors: Takashi Kariya, Toshiki Furutani
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Publication number: 20110102122Abstract: A printed wiring board including a substrate having a first surface and a second surface on the opposite side of the second surface, a first conductive circuit formed on the first surface of the substrate, a second conductive circuit formed on the second surface of the substrate, a magnetic body embedded in the substrate and extending in a thickness direction of the substrate, the magnetic body having a through-hole formed through the magnetic body and extending in the thickness direction of the substrate, and a through-hole conductor formed on an inner surface of the through-hole of the magnetic body such that the first and second conductive circuits are electrically connected to each other through the through-hole conductor.Type: ApplicationFiled: January 6, 2011Publication date: May 5, 2011Applicant: IBIDEN CO., LTD.Inventors: Yasuhiko MANO, Takashi KARIYA, Shinobu KATO
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Publication number: 20110100700Abstract: A multilayer printed wiring board 10 includes: a build-up layer 30 that is formed on a core substrate 20 and has a conductor pattern 32 disposed on an upper surface; a low elastic modulus layer 40 that is formed on the build-up layer 30; lands 52 that are disposed on an upper surface of the low elastic modulus layer 40 and connected via solder bumps 66 to a IC chip 70; and conductor posts 50 that pass through the low elastic modulus layer 40 and electrically connect lands 52 with conductor patterns 32. The conductor posts 50 have the aspect ratio Rasp (height/minimum diameter) of not less than 4 and the minimum diameter exceeding 30 ?m, and the aspect ratio Rasp of external conductor posts 50a, which are positioned at external portions of the low elastic modulus layer 40, is greater than or equal to the aspect ratio Rasp of internal conductor posts 50b, which are positioned at internal portions of the low elastic modulus layer 40.Type: ApplicationFiled: January 5, 2011Publication date: May 5, 2011Applicant: IBIDEN CO., LTD.Inventors: Takashi KARIYA, Toshiki FURUTANI
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Publication number: 20110063811Abstract: A printed wiring board includes a main body having a mounting portion and ground and power supply pads in the mounting portion such that a ground line of a semiconductor device is connected to a ground pad and a power supply line of the device is connected to a power supply pad, and a layered capacitor disposed in the main body and having a high dielectric constant layer and first and second layer electrodes sandwiching the dielectric layer. One of the electrodes is connected to the power supply line and the other electrode is connected to the ground line, the first electrode has a solid pattern including passage holes through which second rod terminals connected to the second electrode pass in a non-contacting manner, and the second electrode has a solid pattern including passage holes through which first rod terminals connected to the first electrode pass in a non-contacting manner.Type: ApplicationFiled: November 18, 2010Publication date: March 17, 2011Applicant: IBIDEN CO., LTD.Inventors: Takashi KARIYA, Akira Mochida
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Publication number: 20110063806Abstract: A circuit wiring board including a wiring substrate, multiple electronic components provided on a surface of the wiring substrate, and a heat resistant substrate accommodated in the wiring substrate and having a core substrate and a built-up wiring layer formed over the core substrate. The built-up wiring layer includes a conductive layer and an interlayer resin insulating layer, and the electronic components are electrically connected to the conductive layer of the built-up wiring layer.Type: ApplicationFiled: November 23, 2010Publication date: March 17, 2011Applicant: IBIDEN CO., LTD.Inventors: Takashi KARIYA, Toshiki Furutani, Takeshi Kawanishi